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| author | seb <seb@pkgsrc.org> | 2004-04-10 16:37:22 +0000 |
|---|---|---|
| committer | seb <seb@pkgsrc.org> | 2004-04-10 16:37:22 +0000 |
| commit | 4db623d9f570e476ffc4b2a8776b3bbfb29260d7 (patch) | |
| tree | 0ae88098f24dd533ed42ee3f423579461c22311a /lang/gcc3 | |
| parent | f78237671addfa77544212b63680b107a7dd4d5d (diff) | |
| download | pkgsrc-4db623d9f570e476ffc4b2a8776b3bbfb29260d7.tar.gz | |
Apply sparc64 fix from gcc cvs via
src/gnu/dist/gcc/gcc/config/sparc/sparc.h revision 1.2.
Bump PKGREVISION of gcc3-c package.
Diffstat (limited to 'lang/gcc3')
| -rw-r--r-- | lang/gcc3/distinfo | 3 | ||||
| -rw-r--r-- | lang/gcc3/patches/patch-ao | 25 |
2 files changed, 27 insertions, 1 deletions
diff --git a/lang/gcc3/distinfo b/lang/gcc3/distinfo index e01c598b9e6..ff44fe66ba8 100644 --- a/lang/gcc3/distinfo +++ b/lang/gcc3/distinfo @@ -1,4 +1,4 @@ -$NetBSD: distinfo,v 1.14 2004/04/10 15:47:08 seb Exp $ +$NetBSD: distinfo,v 1.15 2004/04/10 16:37:22 seb Exp $ SHA1 (gcc-3.3.3.tar.bz2) = a9efbc34c5dd7fc48f7d700461de4fc014968cab Size (gcc-3.3.3.tar.bz2) = 23279245 bytes @@ -13,3 +13,4 @@ SHA1 (patch-ak) = 9df2be9ed9f92218efce073ed0a727c0311630d0 SHA1 (patch-al) = 6294061358e2b618a980e77cbf7bad6231feacbe SHA1 (patch-am) = 8eff72d76b135a9b0318de651341cb08976758b5 SHA1 (patch-an) = c0795339102b4608a3813c3a2d488c71ea972d6f +SHA1 (patch-ao) = b02a4bcf07d67511a337165164e8f344c3303fb7 diff --git a/lang/gcc3/patches/patch-ao b/lang/gcc3/patches/patch-ao new file mode 100644 index 00000000000..7dc5b15d4ec --- /dev/null +++ b/lang/gcc3/patches/patch-ao @@ -0,0 +1,25 @@ +$NetBSD: patch-ao,v 1.1 2004/04/10 16:37:22 seb Exp $ + +--- gcc/config/sparc/sparc.h 23 Jul 2003 02:41:59 -0000 1.1 ++++ gcc/config/sparc/sparc.h 22 Mar 2004 22:56:10 -0000 1.2 +@@ -1233,6 +1233,20 @@ + {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \ + {-1, -1, -1, 0x3f}} /* ALL_REGS */ + ++/* Defines invalid mode changes. Borrowed from pa64-regs.h. ++ ++ SImode loads to floating-point registers are not zero-extended. ++ The definition for LOAD_EXTEND_OP specifies that integer loads ++ narrower than BITS_PER_WORD will be zero-extended. As a result, ++ we inhibit changes from SImode unless they are to a mode that is ++ identical in size. */ ++ ++#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ ++ (TARGET_ARCH64 \ ++ && (FROM) == SImode \ ++ && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ ++ ? reg_classes_intersect_p (CLASS, FP_REGS) : 0) ++ + /* The same information, inverted: + Return the class number of the smallest class containing + reg number REGNO. This could be a conditional expression |