add Verilog-A definitions

3 files changed, 58 insertions, 10 deletions

diff --git a/print/lgrind/Makefile b/print/lgrind/Makefile
index a833ff48d37..d2b357237e7 100644
--- a/print/lgrind/Makefile
+++ b/print/lgrind/Makefile
@@ -1,8 +1,8 @@
-# $NetBSD: Makefile,v 1.12 2002/03/13 17:37:36 fredb Exp $
+# $NetBSD: Makefile,v 1.13 2002/08/27 03:00:12 dmcmahill Exp $
 
 DISTNAME=	lgrind
 PKGNAME=	lgrind-3.5
-PKGREVISION=	1
+PKGREVISION=	2
 CATEGORIES=	print
 MASTER_SITES=	${MASTER_SITE_LOCAL}
 EXTRACT_SUFX=	.tar.bz2
diff --git a/print/lgrind/distinfo b/print/lgrind/distinfo
index 264d16a6ce9..8994ba61c8f 100644
--- a/print/lgrind/distinfo
+++ b/print/lgrind/distinfo
@@ -1,8 +1,8 @@
-$NetBSD: distinfo,v 1.2 2001/04/20 12:41:51 agc Exp $
+$NetBSD: distinfo,v 1.3 2002/08/27 03:00:12 dmcmahill Exp $
 
 SHA1 (lgrind.tar.bz2) = 152d92ccdcb9bc7342f6aec6c4c009d124f7e812
 Size (lgrind.tar.bz2) = 90624 bytes
 SHA1 (patch-aa) = 48955722b024a3d88000db89afaa1b8c83054774
 SHA1 (patch-ab) = cf62c0aafe78806f2c83d8ba8410da9d692dcf7d
 SHA1 (patch-ac) = e6fc5bdebe7c138aad45acd545b63acaed70d356
-SHA1 (patch-ad) = 07a73ed7af99a1fd2cceb16a698b5a541c1dd9cf
+SHA1 (patch-ad) = a475dd078de2d92ffdd23592fd16ae489cec5dee
diff --git a/print/lgrind/patches/patch-ad b/print/lgrind/patches/patch-ad
index c8706549671..2dc82b321ad 100644
--- a/print/lgrind/patches/patch-ad
+++ b/print/lgrind/patches/patch-ad
@@ -1,16 +1,18 @@
-$NetBSD: patch-ad,v 1.1 2001/02/15 07:18:57 dmcmahill Exp $
+$NetBSD: patch-ad,v 1.2 2002/08/27 03:00:13 dmcmahill Exp $
+
+Add Verilog and Verilog-A
 
 --- ../lgrindef.orig	Tue Aug  4 09:01:00 1998
-+++ ../lgrindef	Wed Feb 14 22:34:26 2001
-@@ -685,4 +685,30 @@
++++ ../lgrindef	Mon Aug 26 22:54:31 2002
+@@ -685,4 +685,75 @@
  tk_popup tkwait toplevel trace unknown unset update uplevel upvar while winfo wm:
  
-+# verilog.  Written by Dan McMahill
++# verilog.  Written by Dan McMahill <dmcmahill@netbsd.org>
 +Verilog:\
 +	:pb=\dmodule\d?\p:np=\)\d;:bb=begin\d:be=end\d:\
 +	:cb=/*:ce=*/:sb=":se=\e":\
 +	:tl:ab=//:ae=$:id=_$`:\
-+	:zb=@:ze=@:tb=%%:te=%%:mb=%\$:me=\$%:vb=%\|:ve=\|%:\
++	:tb=%%:te=%%:mb=%\$:me=\$%:vb=%\|:ve=\|%:\
 +	:kw=always and assign attribute begin buf bufif0 bufif1 case casex \
 +	casez cmos deassign default defparam disable edge else end endattribute \
 +	endcase endfunction endmodule endprimitive endspecify \
@@ -31,11 +33,57 @@ $NetBSD: patch-ad,v 1.1 2001/02/15 07:18:57 dmcmahill Exp $
 +	`nounconnected_drive `protect `protected `remove_gatenames `remove_netnames \
 +	`resetall `timescale `unconnected_drive:
 +
++# VerilogA.  Written by Dan McMahill <dmcmahill@netbsd.org>
++#
++# the keywords were from appendix E of
++# the Affirma Verilog-A Language Reference, Dec. 1999
++#
++# the ` compiler directives were from page 11-2 of
++# the Affirma Verilog-A Language Reference, Dec. 1999
++#
++# the $ simulator functions were from chapter 9
++# the Affirma Verilog-A Language Reference, Dec. 1999
++VerilogA:\
++	:pb=\dmodule\d?\p:np=\)\d;:bb=begin\d:be=end\d:\
++	:cb=/*:ce=*/:sb=":se=\e":\
++	:tl:ab=//:ae=$:id=_$`:\
++	:tb=%%:te=%%:mb=%\$:me=\$%:vb=%\|:ve=\|%:\
++	:kw=abs abstol access acos ac_stim always analog analysis and asin \
++	asinh assign atan atan2 atanh begin bound_step branch buf bufif0 \
++	bufif1 case casex \
++	casez cmos cos cosh cross ddt ddt_nature deassign default defparam \
++	disable discipline discontinuity edge else \
++	end enddiscipline  \
++	endcase endfunction endmodule endnature endprimitive endspecify \
++	endtable endtask event exclude exp final_step flicker_noise flow for \
++	force forever fork from function generate ground highz0 highz1 hypot \
++	idt idtmod idt_nature if ifnone inf initial initial_step\
++	inout input integer join laplace_nd laplace_np laplace_zd laplace_zp \
++	large last_crossing ln log macromodule max medium min module nand \
++	nature negedge nmos noise_table nor \
++	not notif0 notif1 or output parameter pmos posedge potential pow \
++	primitive pull0 pull1 \
++	pulldown pullup rcmos real realtime reg release repeat rnmos rpmos rtran \
++	rtranif0 rtranif1 scalared sin sinh slew small specify specparam sqrt \
++	strong0 \
++	strong1 supply0 supply1 table taan tanh task temperature time timer \
++	tran tranif0 tranif1 transition tri tri0 tri1 \
++	triand trior trireg units vectored vt wait wand weak0 weak1 while \
++	white_noise wire wor \
++	xnor xor zi_nd zi_np zi_nd zi_zp \
++	$realtime $temperature $vt $random $dist_uniform $dist_normal \
++	$dist_exponential $dist_poisson $dist_chi_square $dist_t $dist_erlang \
++	$limexp \
++	$strobe $display $pwr $fopen $fstrobe $fdisplay $fclose \
++	$finish $stop \
++	`define `undef `ifdef `include `timescale `resetall `default_nodetype:
++
  
  # JL - Added visbasic 6 Aug 1996. Note: this is not complete!
-@@ -748,4 +774,5 @@
+@@ -748,4 +819,6 @@
  	:pro=prolog:\
  	:m=matlab:\
 +	:v=verilog:\
++	:va=veriloga:\
  	:f=f77:F=f77:for=f77: