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author | dmcmahill <dmcmahill@pkgsrc.org> | 2003-08-24 18:38:06 +0000 |
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committer | dmcmahill <dmcmahill@pkgsrc.org> | 2003-08-24 18:38:06 +0000 |
commit | 9c45065ef259c3ce5400ec849c12bbfe1a251d4e (patch) | |
tree | 3ac898a638403508d1a225c7dab165008965824e /time/pcal | |
parent | b6b0867f942b00c2c45bbf62562c37d654cef4f2 (diff) | |
download | pkgsrc-9c45065ef259c3ce5400ec849c12bbfe1a251d4e.tar.gz |
import covered-0.2.1
Covered is a Verilog code coverage analysis tool that can be useful
for determining how well a diagnostic test suite is covering the
design under test. Typically in the design verification work flow, a
design verification engineer will develop a self-checking test suite
to verify design elements/functions specified by a design's
specification document. When the test suite contains all of the tests
required by the design specification, the test writer may be asking
him/herself, "How much logic in the design is actually being
exercised?", "Does my test suite cover all of the logic under test?",
and "Am I done writing tests for the logic?". When the design
verification gets to this point, it is often useful to get some
metrics for determining logic coverage. This is where a code coverage
utility, such as Covered, is very useful.
Please note that this package is for a stable release version.
There is a seperate package (covered-current) which is made of
development snapshots.
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