summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--cad/verilog-current/Makefile6
-rw-r--r--cad/verilog-current/files/md54
-rw-r--r--cad/verilog-current/files/patch-sum11
-rw-r--r--cad/verilog-current/patches/patch-aa17
-rw-r--r--cad/verilog-current/patches/patch-ab18
-rw-r--r--cad/verilog-current/patches/patch-ac11
-rw-r--r--cad/verilog-current/patches/patch-ae13
-rw-r--r--cad/verilog-current/patches/patch-af11
-rw-r--r--cad/verilog-current/patches/patch-ag11
-rw-r--r--cad/verilog-current/pkg/PLIST4
10 files changed, 88 insertions, 18 deletions
diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile
index 9e1d7a290c7..f4e56cbff54 100644
--- a/cad/verilog-current/Makefile
+++ b/cad/verilog-current/Makefile
@@ -1,8 +1,8 @@
-# $NetBSD: Makefile,v 1.13 2001/03/27 03:19:47 hubertf Exp $
+# $NetBSD: Makefile,v 1.14 2001/03/31 00:00:35 dmcmahill Exp $
#
-DISTNAME= verilog-20010113
-PKGNAME= verilog-current-20010113
+DISTNAME= verilog-20010324
+PKGNAME= verilog-current-20010324
CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/
diff --git a/cad/verilog-current/files/md5 b/cad/verilog-current/files/md5
index a53eb6d2008..590e3623a84 100644
--- a/cad/verilog-current/files/md5
+++ b/cad/verilog-current/files/md5
@@ -1,3 +1,3 @@
-$NetBSD: md5,v 1.11 2001/01/14 19:01:14 dmcmahill Exp $
+$NetBSD: md5,v 1.12 2001/03/31 00:00:35 dmcmahill Exp $
-MD5 (verilog-20010113.tar.gz) = 4d871a15c6422a1de562354175128285
+SHA1 (verilog-20010324.tar.gz) = dd79048cf7582937b64f138064d545ca9f4bbbc2
diff --git a/cad/verilog-current/files/patch-sum b/cad/verilog-current/files/patch-sum
index 1c81adb246d..859fef05cb0 100644
--- a/cad/verilog-current/files/patch-sum
+++ b/cad/verilog-current/files/patch-sum
@@ -1,4 +1,9 @@
-$NetBSD: patch-sum,v 1.10 2000/12/19 18:53:52 dmcmahill Exp $
+$NetBSD: patch-sum,v 1.11 2001/03/31 00:00:35 dmcmahill Exp $
-MD5 (patch-aa) = 2ab80a6d95583009b71b880dc4f264ac
-MD5 (patch-ad) = a9da357e98b2a3ddf6572a0f51b2f5f7
+SHA1 (patch-aa) = a965c134268f33615e3b9914f9a20742fc97ad61
+SHA1 (patch-ab) = 505a8ca954e664f366ec9848e777bad056d57c1c
+SHA1 (patch-ac) = e6ca9502c6c39e2b563db74ee567c54e24c82c96
+SHA1 (patch-ad) = ebd01d8ffbc55d8cd98682e07c22d2e30218d285
+SHA1 (patch-ae) = 901609b4ca3ab726ccc7a88fb2eed6a42532a1ad
+SHA1 (patch-af) = dac5f8c21f53329f3b366aa03d14fd07e9a60396
+SHA1 (patch-ag) = bd981f93aff766cf27463f59b68e20cac0d80431
diff --git a/cad/verilog-current/patches/patch-aa b/cad/verilog-current/patches/patch-aa
index 6d4a5667164..348505d76a5 100644
--- a/cad/verilog-current/patches/patch-aa
+++ b/cad/verilog-current/patches/patch-aa
@@ -1,11 +1,10 @@
-$NetBSD: patch-aa,v 1.5 2000/12/19 18:53:52 dmcmahill Exp $
+$NetBSD: patch-aa,v 1.6 2001/03/31 00:00:35 dmcmahill Exp $
---- tgt-pal/Makefile.in.orig Thu Dec 14 18:37:47 2000
-+++ tgt-pal/Makefile.in Sun Dec 17 07:52:23 2000
-@@ -63,5 +63,5 @@
+--- vvp/vpi_mcd.cc.orig Wed Mar 21 21:24:05 2001
++++ vvp/vpi_mcd.cc Fri Mar 30 09:47:26 2001
+@@ -79,4 +79,5 @@
+ return NULL;
+ }
++static unsigned int vpi_mcd_open_x(char *name, char *mode);
- pal.tgt: $O $(TGTDEPLIBS)
-- $(CC) @shared@ -o $@ $O $(TGTLDFLAGS) -lipal
-+ $(CC) @shared@ -o $@ $O $(TGTLDFLAGS) $(LDFLAGS) -lipal
-
- clean:
+ unsigned int vpi_mcd_open(char *name)
diff --git a/cad/verilog-current/patches/patch-ab b/cad/verilog-current/patches/patch-ab
new file mode 100644
index 00000000000..df9735025c1
--- /dev/null
+++ b/cad/verilog-current/patches/patch-ab
@@ -0,0 +1,18 @@
+$NetBSD: patch-ab,v 1.3 2001/03/31 00:00:35 dmcmahill Exp $
+
+--- vvp/functor.cc.orig Thu Mar 22 00:28:16 2001
++++ vvp/functor.cc Fri Mar 30 09:47:50 2001
+@@ -185,5 +185,5 @@
+ functor_t idxp = functor_index(idx);
+ vvp_ipoint_t next = idxp->port[ipoint_port(idx)];
+- printf(" set %lx to %u\n", idx, oval);
++ printf(" set %lx to %u\n", (unsigned long) idx, oval);
+ functor_set(idx, oval);
+ idx = next;
+@@ -195,5 +195,5 @@
+ for (unsigned idx = 1 ; idx < functor_count ; idx += 1) {
+ functor_t cur = functor_index(idx*4);
+- fprintf(fd, "%10p: out=%x port={%x %x %x %x}\n", idx*4,
++ fprintf(fd, "%10p: out=%x port={%x %x %x %x}\n",(void *) (idx*4),
+ cur->out, cur->port[0], cur->port[1],
+ cur->port[2], cur->port[3]);
diff --git a/cad/verilog-current/patches/patch-ac b/cad/verilog-current/patches/patch-ac
new file mode 100644
index 00000000000..1168ceac530
--- /dev/null
+++ b/cad/verilog-current/patches/patch-ac
@@ -0,0 +1,11 @@
+$NetBSD: patch-ac,v 1.1 2001/03/31 00:00:35 dmcmahill Exp $
+
+--- tgt-vvp/vvp_scope.c.orig Tue Mar 20 20:49:43 2001
++++ tgt-vvp/vvp_scope.c Fri Mar 30 09:54:01 2001
+@@ -51,5 +51,5 @@
+ }
+
+- ivl_scope_children(net, draw_scope, net);
++ ivl_scope_children(net, (ivl_scope_f *) draw_scope, net);
+ return 0;
+ }
diff --git a/cad/verilog-current/patches/patch-ae b/cad/verilog-current/patches/patch-ae
new file mode 100644
index 00000000000..d851b23a47a
--- /dev/null
+++ b/cad/verilog-current/patches/patch-ae
@@ -0,0 +1,13 @@
+$NetBSD: patch-ae,v 1.3 2001/03/31 00:00:35 dmcmahill Exp $
+
+--- vvp/Makefile.in.orig Thu Mar 22 17:37:36 2001
++++ vvp/Makefile.in Fri Mar 30 11:08:42 2001
+@@ -40,6 +40,6 @@
+ STRIP = @STRIP@
+
+-CPPFLAGS = @CPPFLAGS@ @DEFS@ -DMODULE_DIR=\"$(libdir)/ivl\"
+-CXXFLAGS = @CXXFLAGS@ -I. -I$(srcdir)/..
++CPPFLAGS = -I. -I$(srcdir)/.. @CPPFLAGS@ @DEFS@ -DMODULE_DIR=\"$(libdir)/ivl\"
++CXXFLAGS = @CXXFLAGS@
+ LDFLAGS = @LDFLAGS@
+
diff --git a/cad/verilog-current/patches/patch-af b/cad/verilog-current/patches/patch-af
new file mode 100644
index 00000000000..98f343a765f
--- /dev/null
+++ b/cad/verilog-current/patches/patch-af
@@ -0,0 +1,11 @@
+$NetBSD: patch-af,v 1.1 2001/03/31 00:00:35 dmcmahill Exp $
+
+--- tgt-vvp/Makefile.in.orig Thu Mar 22 00:06:21 2001
++++ tgt-vvp/Makefile.in Fri Mar 30 10:45:46 2001
+@@ -47,5 +47,5 @@
+ %.o: %.c
+ @[ -d dep ] || mkdir dep
+- $(CC) -Wall $(CPPFLAGS) -I$(srcdir)/.. -MD -c $< -o $*.o
++ $(CC) -Wall -I$(srcdir)/.. $(CPPFLAGS) -MD -c $< -o $*.o
+ mv $*.d dep
+
diff --git a/cad/verilog-current/patches/patch-ag b/cad/verilog-current/patches/patch-ag
new file mode 100644
index 00000000000..0d90975e7e2
--- /dev/null
+++ b/cad/verilog-current/patches/patch-ag
@@ -0,0 +1,11 @@
+$NetBSD: patch-ag,v 1.1 2001/03/31 00:00:36 dmcmahill Exp $
+
+--- vpi/Makefile.in.orig Mon Mar 19 20:43:16 2001
++++ vpi/Makefile.in Fri Mar 30 11:06:49 2001
+@@ -51,5 +51,5 @@
+ %.o: %.c
+ @[ -d dep ] || mkdir dep
+- $(CC) -Wall $(CPPFLAGS) $(CFLAGS) -I$(srcdir) -I$(srcdir)/.. -MD -c $< -o $*.o
++ $(CC) -Wall -I$(srcdir) -I$(srcdir)/.. $(CPPFLAGS) $(CFLAGS) -MD -c $< -o $*.o
+ mv $*.d dep
+
diff --git a/cad/verilog-current/pkg/PLIST b/cad/verilog-current/pkg/PLIST
index 62238ae2607..2c60efe96cd 100644
--- a/cad/verilog-current/pkg/PLIST
+++ b/cad/verilog-current/pkg/PLIST
@@ -1,5 +1,6 @@
-@comment $NetBSD: PLIST,v 1.7 2000/12/19 18:53:52 dmcmahill Exp $
+@comment $NetBSD: PLIST,v 1.8 2001/03/31 00:00:36 dmcmahill Exp $
bin/iverilog
+bin/vvp
include/ivl_target.h
include/vpi_priv.h
include/vpi_user.h
@@ -18,5 +19,6 @@ lib/ivl/ivlpp
lib/ivl/null.tgt
lib/ivl/pal.tgt
lib/ivl/system.vpi
+lib/ivl/vvp.tgt
man/man1/iverilog.1
@dirrm lib/ivl