8 files changed, 0 insertions, 186 deletions
diff --git a/cad/verilog/DESCR b/cad/verilog/DESCR
deleted file mode 100644
index b59d099759e..00000000000
--- a/cad/verilog/DESCR
+++ /dev/null
@@ -1,12 +0,0 @@
-Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
-compiler, compiling source code writen in Verilog (IEEE-1364) into some target
-format. For batch simulation, the compiler can generate C++ code that is
-compiled and linked with a run time library (called "vvm") then executed as
-a command to run the simulation. For synthesis, the compiler generates
-netlists in the desired format.
-
-The compiler proper is intended to parse and elaborate design descriptions
-written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
-complex standard, so it will take some time for it to get there, but that's
-the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well,
-and some -1999 features will creep in.
diff --git a/cad/verilog/Makefile b/cad/verilog/Makefile
deleted file mode 100644
index 9fd5d79e591..00000000000
--- a/cad/verilog/Makefile
+++ /dev/null
@@ -1,35 +0,0 @@
-# $NetBSD: Makefile,v 1.43 2016/10/08 22:30:43 kamil Exp $
-#
-
-DISTNAME=	verilog-10.1.1
-CATEGORIES=	cad
-MASTER_SITES=	ftp://icarus.com/pub/eda/verilog/v10/
-# FTP has newer release than GitHub tag
-#MASTER_SITES=	${MASTER_SITE_GITHUB:=steveicarus/}
-#GITHUB_TAG=	v${PKGVERSION_NOREV:S/./_/}
-
-MAINTAINER=	dmcmahill@NetBSD.org
-HOMEPAGE=	http://iverilog.icarus.com/
-COMMENT=	Verilog simulation and synthesis tool (stable release version)
-LICENSE=	gnu-gpl-v2
-
-USE_LANGUAGES=	c c++
-
-GNU_CONFIGURE=		yes
-USE_TOOLS+=		gmake bison lex
-TEST_TARGET=		check
-
-INSTALLATION_DIRS+=	share/doc/ivl
-
-# Additional files
-post-install:
-	cd ${WRKSRC}; ${INSTALL_DATA} \
-		QUICK_START.txt \
-		README.txt      \
-	${DESTDIR}${PREFIX}/share/doc/ivl
-
-.include "../../devel/gperf/buildlink3.mk"
-.include "../../devel/zlib/buildlink3.mk"
-.include "../../archivers/bzip2/buildlink3.mk"
-.include "../../mk/readline.buildlink3.mk"
-.include "../../mk/bsd.pkg.mk"
diff --git a/cad/verilog/PLIST b/cad/verilog/PLIST
deleted file mode 100644
index bac4b0fda9a..00000000000
--- a/cad/verilog/PLIST
+++ /dev/null
@@ -1,58 +0,0 @@
-@comment $NetBSD: PLIST,v 1.11 2016/10/08 22:30:43 kamil Exp $
-bin/iverilog
-bin/iverilog-vpi
-bin/vvp
-include/iverilog/_pli_types.h
-include/iverilog/acc_user.h
-include/iverilog/ivl_target.h
-include/iverilog/sv_vpi_user.h
-include/iverilog/veriuser.h
-include/iverilog/vpi_user.h
-lib/ivl/blif-s.conf
-lib/ivl/blif.conf
-lib/ivl/blif.tgt
-lib/ivl/cadpli.vpl
-lib/ivl/include/constants.vams
-lib/ivl/include/disciplines.vams
-lib/ivl/ivl
-lib/ivl/ivlpp
-lib/ivl/null-s.conf
-lib/ivl/null.conf
-lib/ivl/null.tgt
-lib/ivl/pcb-s.conf
-lib/ivl/pcb.conf
-lib/ivl/pcb.tgt
-lib/ivl/sizer-s.conf
-lib/ivl/sizer.conf
-lib/ivl/sizer.tgt
-lib/ivl/stub-s.conf
-lib/ivl/stub.conf
-lib/ivl/stub.tgt
-lib/ivl/system.sft
-lib/ivl/system.vpi
-lib/ivl/v2005_math.sft
-lib/ivl/v2005_math.vpi
-lib/ivl/v2009.sft
-lib/ivl/v2009.vpi
-lib/ivl/va_math.sft
-lib/ivl/va_math.vpi
-lib/ivl/vhdl-s.conf
-lib/ivl/vhdl.conf
-lib/ivl/vhdl.tgt
-lib/ivl/vhdl_sys.sft
-lib/ivl/vhdl_sys.vpi
-lib/ivl/vhdlpp
-lib/ivl/vlog95-s.conf
-lib/ivl/vlog95.conf
-lib/ivl/vlog95.tgt
-lib/ivl/vpi_debug.vpi
-lib/ivl/vvp-s.conf
-lib/ivl/vvp.conf
-lib/ivl/vvp.tgt
-lib/libveriuser.a
-lib/libvpi.a
-man/man1/iverilog-vpi.1
-man/man1/iverilog.1
-man/man1/vvp.1
-share/doc/ivl/QUICK_START.txt
-share/doc/ivl/README.txt
diff --git a/cad/verilog/buildlink3.mk b/cad/verilog/buildlink3.mk
deleted file mode 100644
index 2f8fe04e793..00000000000
--- a/cad/verilog/buildlink3.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-# $NetBSD: buildlink3.mk,v 1.11 2016/10/08 22:30:43 kamil Exp $
-
-BUILDLINK_TREE+=	verilog
-
-.if !defined(VERILOG_BUILDLINK3_MK)
-VERILOG_BUILDLINK3_MK:=
-
-BUILDLINK_API_DEPENDS.verilog+=	verilog>=10.1.1
-BUILDLINK_PKGSRCDIR.verilog?=	../../cad/verilog
-
-.include "../../devel/gperf/buildlink3.mk"
-.include "../../devel/zlib/buildlink3.mk"
-.include "../../archivers/bzip2/buildlink3.mk"
-.endif	# VERILOG_BUILDLINK3_MK
-
-BUILDLINK_TREE+=	-verilog
diff --git a/cad/verilog/distinfo b/cad/verilog/distinfo
deleted file mode 100644
index 2ba24e91035..00000000000
--- a/cad/verilog/distinfo
+++ /dev/null
@@ -1,9 +0,0 @@
-$NetBSD: distinfo,v 1.21 2016/10/08 22:30:43 kamil Exp $
-
-SHA1 (verilog-10.1.1.tar.gz) = 7f4cead8cabb90cc4525951357c43866ca710749
-RMD160 (verilog-10.1.1.tar.gz) = 77c933b712ab027b13a81e3eead7ee4f565741b7
-SHA512 (verilog-10.1.1.tar.gz) = a57fdce3d870be8ce39eb3050dabd5a2d4d491c657b85ccbf775bef7fa9a6889a18bf4d2508341ef2cc17d872b5d6c802d4fd8585e4ec7952526699ebb24bfac
-Size (verilog-10.1.1.tar.gz) = 1684925 bytes
-SHA1 (patch-aa) = cf075110416f6db0892129796cd83b8ae8de55fa
-SHA1 (patch-ad) = bf7d227ed3b321021d8aff54cd008f4b2a1557b9
-SHA1 (patch-cadpli_Makefile) = ed21a5f529ac449c26b831cbd5fde052d9ed5466
diff --git a/cad/verilog/patches/patch-aa b/cad/verilog/patches/patch-aa
deleted file mode 100644
index bdd0b7e06ec..00000000000
--- a/cad/verilog/patches/patch-aa
+++ /dev/null
@@ -1,14 +0,0 @@
-$NetBSD: patch-aa,v 1.13 2014/01/07 09:43:54 mef Exp $
-
-gcc44 fixes
-
---- elab_net.cc.orig	2010-09-27 17:42:32.000000000 +0000
-+++ elab_net.cc
-@@ -26,6 +26,7 @@
- 
- # include  <cstdlib>
- # include  <cstring>
-+# include  <memory>
- # include  <iostream>
- # include  "ivl_assert.h"
- 
diff --git a/cad/verilog/patches/patch-ad b/cad/verilog/patches/patch-ad
deleted file mode 100644
index 0de062a87b6..00000000000
--- a/cad/verilog/patches/patch-ad
+++ /dev/null
@@ -1,25 +0,0 @@
-$NetBSD: patch-ad,v 1.11 2014/01/07 09:43:54 mef Exp $
-
-make sure no one sneaks a -O* in on us via one of these variables
-set in the environment
-
---- Makefile.in.orig	2013-08-20 04:10:31.000000000 +0900
-+++ Makefile.in	2013-12-20 11:35:09.000000000 +0900
-@@ -222,6 +222,17 @@
- 
- lexor.o: lexor.cc parse.h
- 
-+# make sure no one sneaks a -O* in on us via one of these variables
-+# set in the environment
-+CXX_NOOPT=$(CXX:-O%=)
-+CPPFLAGS_NOOPT=$(CPPFLAGS:-O%=)
-+CXXFLAGS_NOOPT=$(CXXFLAGS:-O%=)
-+
-+parse.o: parse.cc
-+	@[ -d dep ] || mkdir dep
-+	$(CXX_NOOPT) $(CPPFLAGS_NOOPT) $(CXXFLAGS_NOOPT) -MD -c $< -o $*.o
-+	mv $*.d dep/$*.d
-+
- parse.o: parse.cc
- 
- # Build this in two steps to avoid parallel build issues (see pr3462585)
diff --git a/cad/verilog/patches/patch-cadpli_Makefile b/cad/verilog/patches/patch-cadpli_Makefile
deleted file mode 100644
index 90143b65ff9..00000000000
--- a/cad/verilog/patches/patch-cadpli_Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-$NetBSD: patch-cadpli_Makefile,v 1.1 2014/01/07 09:43:54 mef Exp $
-
-gcc -std=gnu99 -shared -L/usr/lib -Wl,-R/usr/lib -L/usr/pkg/lib -Wl,-R/usr/pkg/lib -o cadpli.vpl cadpli.o ../libveriuser/libveriuser.o -L../vvp -lvpi
-mkdir: dep: Not a directory
-Makefile:52: recipe for target 'dep' failed
-
---- cadpli/Makefile.in~	2013-08-20 04:10:31.000000000 +0900
-+++ cadpli/Makefile.in	2013-12-20 22:03:29.000000000 +0900
-@@ -51,7 +51,7 @@ check: all
- dep:
- 	mkdir dep
- 
--%.o: %.c
-+%.o: %.c dep
- 	$(CC) $(CPPFLAGS) $(CFLAGS) @DEPENDENCY_FLAG@ -c $<
- 	mv $*.d dep
-