5 files changed, 92 insertions, 1 deletions
diff --git a/cad/verilog/files/patch-sum b/cad/verilog/files/patch-sum
index 404604a34a4..73dd42c4b10 100644
--- a/cad/verilog/files/patch-sum
+++ b/cad/verilog/files/patch-sum
@@ -1,3 +1,7 @@
-$NetBSD: patch-sum,v 1.7 2001/02/04 15:36:50 dmcmahill Exp $
+$NetBSD: patch-sum,v 1.8 2001/02/07 18:26:16 dmcmahill Exp $
 
+MD5 (patch-aa) = 7e8332be1ae683790ab7386cd2fc80c7
+MD5 (patch-ab) = c8fe631f09455b03796c6a63ee3a1952
+MD5 (patch-ac) = b046eabfcc11ba9d8ecb1796fc0ee055
 MD5 (patch-ad) = a9da357e98b2a3ddf6572a0f51b2f5f7
+MD5 (patch-ae) = 95d0a6681d7868f6269423e447e995bf
diff --git a/cad/verilog/patches/patch-aa b/cad/verilog/patches/patch-aa
new file mode 100644
index 00000000000..d762afcd46e
--- /dev/null
+++ b/cad/verilog/patches/patch-aa
@@ -0,0 +1,54 @@
+$NetBSD: patch-aa,v 1.5 2001/02/07 18:26:17 dmcmahill Exp $
+
+--- tgt-null/null.c.orig	Fri Dec  1 23:50:32 2000
++++ tgt-null/null.c	Sun Feb  4 12:41:40 2001
+@@ -25,5 +25,5 @@
+  */
+ 
+-# include  <ivl_target.h>
++# include  "ivl_target.h"
+ 
+ 
+--- tgt-pal/enables.c.orig	Fri Dec  8 22:42:52 2000
++++ tgt-pal/enables.c	Sun Feb  4 12:41:50 2001
+@@ -20,3 +20,3 @@
+ 
+-# include  <ivl_target.h>
++# include  "ivl_target.h"
+ # include  <assert.h>
+--- tgt-pal/fit_log.c.orig	Thu Dec 14 18:37:47 2000
++++ tgt-pal/fit_log.c	Sun Feb  4 12:41:59 2001
+@@ -21,5 +21,5 @@
+ #endif
+ 
+-# include  <ivl_target.h>
++# include  "ivl_target.h"
+ # include  <stdio.h>
+ # include  <stdlib.h>
+--- tgt-pal/fit_reg.c.orig	Sun Jan 14 19:05:39 2001
++++ tgt-pal/fit_reg.c	Sun Feb  4 12:42:08 2001
+@@ -21,5 +21,5 @@
+ #endif
+ 
+-# include  <ivl_target.h>
++# include  "ivl_target.h"
+ # include  <stdio.h>
+ # include  <assert.h>
+--- tgt-stub/stub.c.orig	Sun Jan 14 19:47:02 2001
++++ tgt-stub/stub.c	Sun Feb  4 12:42:21 2001
+@@ -28,5 +28,5 @@
+  */
+ 
+-# include  <ivl_target.h>
++# include  "ivl_target.h"
+ # include  <stdio.h>
+ 
+--- tgt-verilog/verilog.c.orig	Sun Jan 14 19:05:39 2001
++++ tgt-verilog/verilog.c	Wed Feb  7 10:48:53 2001
+@@ -27,5 +27,5 @@
+  */
+ 
+-# include  <ivl_target.h>
++# include  "ivl_target.h"
+ # include  <stdio.h>
+ # include  <assert.h>
diff --git a/cad/verilog/patches/patch-ab b/cad/verilog/patches/patch-ab
new file mode 100644
index 00000000000..fb8d2291762
--- /dev/null
+++ b/cad/verilog/patches/patch-ab
@@ -0,0 +1,11 @@
+$NetBSD: patch-ab,v 1.5 2001/02/07 18:26:17 dmcmahill Exp $
+
+--- tgt-verilog/Makefile.in.orig	Thu Dec 14 18:38:04 2000
++++ tgt-verilog/Makefile.in	Wed Feb  7 11:12:00 2001
+@@ -48,5 +48,5 @@
+ %.o: %.c
+ 	@[ -d dep ] || mkdir dep
+-	$(CC) -Wall $(CPPFLAGS) -I$(srcdir)/.. -MD -c $< -o $*.o
++	$(CC) -Wall -I$(srcdir)/.. $(CPPFLAGS) -MD -c $< -o $*.o
+ 	mv $*.d dep
+ 
diff --git a/cad/verilog/patches/patch-ac b/cad/verilog/patches/patch-ac
new file mode 100644
index 00000000000..38c8f827517
--- /dev/null
+++ b/cad/verilog/patches/patch-ac
@@ -0,0 +1,11 @@
+$NetBSD: patch-ac,v 1.5 2001/02/07 18:26:17 dmcmahill Exp $
+
+--- tgt-stub/Makefile.in.orig	Thu Dec 14 18:38:04 2000
++++ tgt-stub/Makefile.in	Wed Feb  7 12:25:22 2001
+@@ -48,5 +48,5 @@
+ %.o: %.c
+ 	@[ -d dep ] || mkdir dep
+-	$(CC) -Wall $(CPPFLAGS) -I$(srcdir)/.. -MD -c $< -o $*.o
++	$(CC) -Wall -I$(srcdir)/.. $(CPPFLAGS)  -MD -c $< -o $*.o
+ 	mv $*.d dep
+ 
diff --git a/cad/verilog/patches/patch-ae b/cad/verilog/patches/patch-ae
new file mode 100644
index 00000000000..f885662d8fe
--- /dev/null
+++ b/cad/verilog/patches/patch-ae
@@ -0,0 +1,11 @@
+$NetBSD: patch-ae,v 1.4 2001/02/07 18:26:17 dmcmahill Exp $
+
+--- tgt-pal/Makefile.in.orig	Wed Jan 17 22:09:45 2001
++++ tgt-pal/Makefile.in	Wed Feb  7 12:44:30 2001
+@@ -48,5 +48,5 @@
+ %.o: %.c
+ 	@[ -d dep ] || mkdir dep
+-	$(CC) -Wall $(CPPFLAGS) -I$(srcdir)/.. -MD -c $< -o $*.o
++	$(CC) -Wall -I$(srcdir)/.. $(CPPFLAGS) -MD -c $< -o $*.o
+ 	mv $*.d dep
+