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Diffstat (limited to 'cad/MyHDL-iverilog/DESCR')
| -rw-r--r-- | cad/MyHDL-iverilog/DESCR | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/cad/MyHDL-iverilog/DESCR b/cad/MyHDL-iverilog/DESCR new file mode 100644 index 00000000000..fd819237dc9 --- /dev/null +++ b/cad/MyHDL-iverilog/DESCR @@ -0,0 +1,7 @@ +MyHDL is a Python package for using Python as a hardware +description language. Popular hardware description languages, like +Verilog and VHDL, are compiled languages. MyHDL with Python +can be viewed as a "scripting language" counterpart of such +languages. However, Python is more accurately described as a very +high level language (VHLL). MyHDL users have access to the +amazing power and elegance of Python for their modeling work. |