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Diffstat (limited to 'cad/MyHDL-iverilog/Makefile')
| -rw-r--r-- | cad/MyHDL-iverilog/Makefile | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/cad/MyHDL-iverilog/Makefile b/cad/MyHDL-iverilog/Makefile new file mode 100644 index 00000000000..4691dc1feee --- /dev/null +++ b/cad/MyHDL-iverilog/Makefile @@ -0,0 +1,20 @@ +# $NetBSD: Makefile,v 1.1.1.1 2006/02/10 17:05:03 drochner Exp $ +# + +DISTNAME= myhdl-0.5 +PKGNAME= MyHDL-iverilog-0.5 +CATEGORIES= cad python +MASTER_SITES= ${MASTER_SITE_SOURCEFORGE:=myhdl/} + +MAINTAINER= tech-pkg@NetBSD.org +HOMEPAGE= http://jandecaluwe.com/Tools/MyHDL/Overview.html +COMMENT= Icarus Verilog cosimulation support for py-MyHDL + +BUILD_DIRS+= cosimulation/icarus + +do-install: + ${INSTALL_DATA} ${WRKSRC}/cosimulation/icarus/myhdl.vpi \ + ${PREFIX}/lib/ivl + +.include "../../cad/verilog/buildlink3.mk" +.include "../../mk/bsd.pkg.mk" |