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-rw-r--r--cad/MyHDL-iverilog/Makefile4
1 files changed, 2 insertions, 2 deletions
diff --git a/cad/MyHDL-iverilog/Makefile b/cad/MyHDL-iverilog/Makefile
index 4691dc1feee..c41502dd88d 100644
--- a/cad/MyHDL-iverilog/Makefile
+++ b/cad/MyHDL-iverilog/Makefile
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile,v 1.1.1.1 2006/02/10 17:05:03 drochner Exp $
+# $NetBSD: Makefile,v 1.2 2006/03/04 21:29:01 jlam Exp $
#
DISTNAME= myhdl-0.5
@@ -6,7 +6,7 @@ PKGNAME= MyHDL-iverilog-0.5
CATEGORIES= cad python
MASTER_SITES= ${MASTER_SITE_SOURCEFORGE:=myhdl/}
-MAINTAINER= tech-pkg@NetBSD.org
+MAINTAINER= pkgsrc-users@NetBSD.org
HOMEPAGE= http://jandecaluwe.com/Tools/MyHDL/Overview.html
COMMENT= Icarus Verilog cosimulation support for py-MyHDL