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Diffstat (limited to 'cad/verilog-current/DESCR')
| -rw-r--r-- | cad/verilog-current/DESCR | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/cad/verilog-current/DESCR b/cad/verilog-current/DESCR new file mode 100644 index 00000000000..813cc45415b --- /dev/null +++ b/cad/verilog-current/DESCR @@ -0,0 +1,16 @@ +Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a +compiler, compiling source code writen in Verilog (IEEE-1364) into some target +format. For batch simulation, the compiler can generate C++ code that is +compiled and linked with a run time library (called "vvm") then executed as +a command to run the simulation. For synthesis, the compiler generates +netlists in the desired format. + +The compiler proper is intended to parse and elaborate design descriptions +written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and +complex standard, so it will take some time for it to get there, but that's +the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well, +and some -1999 features will creep in. + +Please note that this package is a development snapshot and while it contains +the latest and greatest features, it may be buggy as well. There is a seperate +verilog package which is made of the stable releases. |