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-rw-r--r--cad/verilog/Makefile4
1 files changed, 2 insertions, 2 deletions
diff --git a/cad/verilog/Makefile b/cad/verilog/Makefile
index aa28bad22e8..e823549bbcc 100644
--- a/cad/verilog/Makefile
+++ b/cad/verilog/Makefile
@@ -1,11 +1,11 @@
-# $NetBSD: Makefile,v 1.13 2002/12/15 01:57:12 dmcmahill Exp $
+# $NetBSD: Makefile,v 1.14 2003/07/17 21:25:26 grant Exp $
#
DISTNAME= verilog-0.7
CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v0.7/
-MAINTAINER= dmcmahill@netbsd.org
+MAINTAINER= dmcmahill@NetBSD.org
HOMEPAGE= http://icarus.com/eda/verilog/index.html
COMMENT= Verilog simulation and synthesis tool (stable release version)