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-rw-r--r--cad/verilog/Makefile3
1 files changed, 2 insertions, 1 deletions
diff --git a/cad/verilog/Makefile b/cad/verilog/Makefile
index 5a7d837c965..80c4a0aac8e 100644
--- a/cad/verilog/Makefile
+++ b/cad/verilog/Makefile
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile,v 1.5 2001/02/04 15:36:49 dmcmahill Exp $
+# $NetBSD: Makefile,v 1.6 2001/02/16 13:46:29 wiz Exp $
#
DISTNAME= verilog-0.4
@@ -7,6 +7,7 @@ MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v0.4/
MAINTAINER= dmcmahill@netbsd.org
HOMEPAGE= http://icarus.com/eda/verilog/index.html
+COMMENT= Verilog simulation and synthesis tool (stable release version)
BUILD_DEPENDS+= bison:../../devel/bison
BUILD_DEPENDS+= gperf:../../devel/gperf