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-rw-r--r--cad/verilog/Makefile4
1 files changed, 2 insertions, 2 deletions
diff --git a/cad/verilog/Makefile b/cad/verilog/Makefile
index 67728beb75b..b3736615349 100644
--- a/cad/verilog/Makefile
+++ b/cad/verilog/Makefile
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile,v 1.10 2001/08/04 01:20:43 dmcmahill Exp $
+# $NetBSD: Makefile,v 1.11 2001/09/27 23:17:47 jlam Exp $
#
DISTNAME= verilog-0.5
@@ -9,7 +9,7 @@ MAINTAINER= dmcmahill@netbsd.org
HOMEPAGE= http://icarus.com/eda/verilog/index.html
COMMENT= Verilog simulation and synthesis tool (stable release version)
-BUILD_DEPENDS+= bison-*:../../devel/bison
+BUILD_DEPENDS+= bison-[0-9]*:../../devel/bison
BUILD_DEPENDS+= gperf-2.7.2:../../devel/gperf
#
# turn this back on when ipal comes along a little further