diff options
Diffstat (limited to 'cad')
| -rw-r--r-- | cad/verilog/Makefile | 11 | ||||
| -rw-r--r-- | cad/verilog/PLIST | 15 | ||||
| -rw-r--r-- | cad/verilog/distinfo | 10 | ||||
| -rw-r--r-- | cad/verilog/patches/patch-aa | 12 | ||||
| -rw-r--r-- | cad/verilog/patches/patch-ab | 13 | ||||
| -rw-r--r-- | cad/verilog/patches/patch-ad | 16 |
6 files changed, 32 insertions, 45 deletions
diff --git a/cad/verilog/Makefile b/cad/verilog/Makefile index c38b858bb67..10ed0dc6536 100644 --- a/cad/verilog/Makefile +++ b/cad/verilog/Makefile @@ -1,9 +1,9 @@ -# $NetBSD: Makefile,v 1.18 2004/03/22 00:15:06 dmcmahill Exp $ +# $NetBSD: Makefile,v 1.19 2004/10/14 22:29:04 dmcmahill Exp $ # -DISTNAME= verilog-0.7 +DISTNAME= verilog-0.8 CATEGORIES= cad -MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v0.7/ +MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v0.8/ MAINTAINER= dmcmahill@NetBSD.org HOMEPAGE= http://icarus.com/eda/verilog/index.html @@ -13,7 +13,6 @@ PKG_INSTALLATION_TYPES= overwrite pkgviews USE_BUILDLINK3= yes BUILD_DEPENDS+= bison-[0-9]*:../../devel/bison -BUILD_DEPENDS+= gperf>=2.7.2:../../devel/gperf CONFLICTS+= verilog-current-[0-9]* @@ -24,4 +23,8 @@ YACC= ${LOCALBASE}/bin/bison TEST_DIRS= ${WRKSRC} TEST_TARGET= check +.include "../../devel/zlib/buildlink3.mk" +.include "../../archivers/bzip2/buildlink3.mk" +.include "../../devel/gperf/buildlink3.mk" +.include "../../devel/readline/buildlink3.mk" .include "../../mk/bsd.pkg.mk" diff --git a/cad/verilog/PLIST b/cad/verilog/PLIST index 67766e16766..5fa45d2c436 100644 --- a/cad/verilog/PLIST +++ b/cad/verilog/PLIST @@ -1,21 +1,32 @@ -@comment $NetBSD: PLIST,v 1.3 2002/12/15 01:57:12 dmcmahill Exp $ +@comment $NetBSD: PLIST,v 1.4 2004/10/14 22:29:04 dmcmahill Exp $ bin/iverilog bin/iverilog-vpi bin/vvp +include/_pli_types.h include/acc_user.h include/ivl_target.h include/veriuser.h include/vpi_user.h lib/libveriuser.a lib/libvpi.a +lib/ivl/cadpli.vpl +lib/ivl/fpga-s.conf +lib/ivl/fpga.conf lib/ivl/fpga.tgt lib/ivl/ivl -lib/ivl/iverilog.conf lib/ivl/ivlpp +lib/ivl/null-s.conf +lib/ivl/null.conf lib/ivl/null.tgt +lib/ivl/system.sft lib/ivl/system.vpi +lib/ivl/vvp-s.conf +lib/ivl/vvp.conf lib/ivl/vvp.tgt +lib/ivl/xnf-s.conf +lib/ivl/xnf.conf man/man1/iverilog.1 +man/man1/iverilog-fpga.1 man/man1/iverilog-vpi.1 man/man1/vvp.1 @dirrm lib/ivl diff --git a/cad/verilog/distinfo b/cad/verilog/distinfo index ee8406e2df1..8f5b2baf522 100644 --- a/cad/verilog/distinfo +++ b/cad/verilog/distinfo @@ -1,7 +1,5 @@ -$NetBSD: distinfo,v 1.6 2004/01/02 14:01:28 jmmv Exp $ +$NetBSD: distinfo,v 1.7 2004/10/14 22:29:04 dmcmahill Exp $ -SHA1 (verilog-0.7.tar.gz) = e7e88078b3232ccc888db5c94bdbc06801ee85cb -Size (verilog-0.7.tar.gz) = 846998 bytes -SHA1 (patch-aa) = e1799f0eedc7a966ac43c6f7f216a3ccc1e5570f -SHA1 (patch-ab) = 236ba9135e1190896e69ecb2fb16b7b2c4dcc3bb -SHA1 (patch-ad) = 3c035d32d011d81520e428e3dd9adae435fc63e7 +SHA1 (verilog-0.8.tar.gz) = e9f00a6a6d0a67530678a0ccf949dbb3d94126c5 +Size (verilog-0.8.tar.gz) = 1371542 bytes +SHA1 (patch-ad) = ef3fe90fb096b96807b2e5766f3ac6849867352a diff --git a/cad/verilog/patches/patch-aa b/cad/verilog/patches/patch-aa deleted file mode 100644 index 13d384e1936..00000000000 --- a/cad/verilog/patches/patch-aa +++ /dev/null @@ -1,12 +0,0 @@ -$NetBSD: patch-aa,v 1.7 2004/01/02 14:01:28 jmmv Exp $ - ---- load_module.cc.orig 2002-08-12 03:34:59.000000000 +0200 -+++ load_module.cc -@@ -24,6 +24,7 @@ - # include "util.h" - # include "parse_api.h" - # include "compiler.h" -+# include <cassert> - # include <iostream> - # include <map> - # include <string> diff --git a/cad/verilog/patches/patch-ab b/cad/verilog/patches/patch-ab deleted file mode 100644 index 934bb5ba3c5..00000000000 --- a/cad/verilog/patches/patch-ab +++ /dev/null @@ -1,13 +0,0 @@ -$NetBSD: patch-ab,v 1.7 2004/01/02 14:01:28 jmmv Exp $ - ---- PUdp.h.orig 2002-08-12 03:34:58.000000000 +0200 -+++ PUdp.h -@@ -29,7 +29,7 @@ - - class PExpr; - --svector<string>::svector<string>(unsigned size) -+inline svector<string>::svector<string>(unsigned size) - : nitems_(size), items_(new string[size]) - { - } diff --git a/cad/verilog/patches/patch-ad b/cad/verilog/patches/patch-ad index eabde9cbc2f..d449d143ae1 100644 --- a/cad/verilog/patches/patch-ad +++ b/cad/verilog/patches/patch-ad @@ -1,13 +1,12 @@ -$NetBSD: patch-ad,v 1.6 2001/08/04 01:20:44 dmcmahill Exp $ +$NetBSD: patch-ad,v 1.7 2004/10/14 22:29:04 dmcmahill Exp $ -work around a c++ -O2 bug which is present on at least sparc -and pmax using egcs-1.1.1 - ---- Makefile.in.orig Sun Mar 25 00:59:46 2001 -+++ Makefile.in Wed May 16 09:38:37 2001 -@@ -143,5 +143,14 @@ +--- Makefile.in.orig 2003-06-25 03:48:39.000000000 +0200 ++++ Makefile.in 2003-07-12 19:11:41.000000000 +0200 +@@ -170,7 +170,17 @@ + lexor.o: lexor.cc parse.h ++# work around buggy compilers when compiling the parser with optimization +# make sure no one sneaks a -O* in on us via one of these variables +# set in the environment +CXX_NOOPT=$(CXX:-O%=) @@ -19,4 +18,5 @@ and pmax using egcs-1.1.1 + $(CXX_NOOPT) $(CPPFLAGS_NOOPT) $(CXXFLAGS_NOOPT) -MD -c $< -o $*.o + mv $*.d dep/$*.d - parse.h parse.cc: $(srcdir)/parse.y + parse.cc: $(srcdir)/parse.y + $(YACC) --verbose -t -p VL -d -o parse.cc $(srcdir)/parse.y |