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+This is SWARM - SoftWare ARM.
+
+The initial stage in this process is implement a plain software model
+of the basic ARM. There are, of course, already software models of
+the ARM available, so why do another one? Well, this one will need to
+allow the instruction set to be modified at run time, and provide not
+just an execution environment, but also a way of monitoring things
+like cache hits.
+
+To this end a hierarchical model of an ARM CPU has been implemented in
+C++. It currently supports:
+
++ Arm 6 based core. Currently able to handle data processing
+instructions, word/byte load and stores, load/store multiple,
+branches, 32 bit multiplication, and SWIs.
++ Support for plugging in different caches - be they unified or
+separate I & D caches. Currently only a direct mapped cache is
+implemented.
++ Compile for SWARM using ARM targeted gcc.