| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2006-05-04 | update MyHDL to 0.5.1 | drochner | 1 | -5/+5 | |
| There is no usable changelog; I've found one real bug closed in the tracker: A verilog '>>>' is generated as appropriate for signed numbers. | |||||
| 2006-02-10 | import MyHDL-gplcver-0.5, a GPL Cver vpi module to support cosimulation | drochner | 1 | -0/+6 | |
| from py-MyHDL | |||||
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index : pkgsrc | |
| [no description] | Dyson |
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