pkgsrc - [no description]

Age	Commit message (Collapse)	Author	Files	Lines
2006-05-04	update MyHDL to 0.5.1	drochner	1	-4/+4
	There is no usable changelog; I've found one real bug closed in the tracker: A verilog '>>>' is generated as appropriate for signed numbers.
2006-02-10	import MyHDL-iverilog-0.5, an Icarus Verilog vpi module to support cosimulation	drochner	1	-0/+5
	from py-MyHDL