| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2006-07-08 | Change the format of BUILDLINK_ORDER to contain depth information as well, | jlam | 1 | -2/+2 |
| 2006-07-08 | Track information in a new variable BUILDLINK_ORDER that informs us | jlam | 1 | -1/+2 |
| 2006-05-21 | Removed default comment. | rillig | 1 | -11/+1 |
| 2006-04-06 | Over 1200 files touched but no revisions bumped :) | reed | 1 | -2/+2 |
| 2006-02-10 | import GPL Cver 2.11a, another Verilog simulator | drochner | 1 | -0/+28 |
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index : pkgsrc | |
| [no description] | Dyson |
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