pkgsrc - [no description]

Age	Commit message (Collapse)	Author	Files	Lines
2006-05-04	update MyHDL to 0.5.1	drochner	1	-4/+1
	There is no usable changelog; I've found one real bug closed in the tracker: A verilog '>>>' is generated as appropriate for signed numbers.
2006-02-10	update to 0.5	drochner	1	-1/+10
	major changes: -supports Python decorator syntax for generators (needs 2.4) -intbv() doesn't have a default anymore -many improvements to Verilog conversion
2005-01-05	update to 0.4.1	drochner	1	-34/+65
	changes: * VCD output for waveform viewing - function additions - needs Python 2.3, 2.4 is OK * Conversion to Verilog to provide a path to implementation * Added cosimulation support for the cver Verilog simulator. - bugfixes
2003-09-14	hange extension.mk to also install optimized files for distutils packages.	recht	1	-1/+14
	Inspired by FreeBSD "ports". Fix the PLISTs accordingly. Also, while at it, remove now obsolete compileall.py calls in post-install targets and insure that extension.mk is in included before builinlinks of other Python modules. Discussed with/ok'ed by drochner@.
2003-06-05	a library which uses Python as a hardware description language, using	drochner	1	-0/+28
	the new generator constructs (like pysim, at a first glance)