| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
last packaged snapshot. Those are:
--------------------------------------------------
Release Notes for Icarus Verilog Snapshot 20060215
--------------------------------------------------
* Part select of memory words should now work according to
Verilog-2001. This also led to some cleanup of the handling of types
internally, as well as some infrastructure for general arrays.
* Minor fix to parsing of (* *) attributes.
* Fix rounding of reals to integers.
* Clean up some of the vvp engine related to memories. Remove some
dead instructions.
--------------------------------------------------
Release Notes for Icarus Verilog Snapshot 20060409
--------------------------------------------------
the most substantial difference in this snapshot the first signs of
generate support. The compiler now supports generate loops and has
been tested with examples that include wires and gates within the
generate scheme. The regression test suite has very few generate
tests, so any concise self-testing test programs that use generate
would be helpful.
Also, instance arrays that use overridden parameters now work
properly.
Task arguments are a bit more flexible in order to support vendor
(notably Xilinx) models that use more interesting task arguments.
Runtime support for bi-directional ports had some bugs fixed, along
with some other minor run-time bugs. Also, the runtime gains support
for typed parameters. And also, there are some new runtime callbacks
for events and memories.
Parameters had a few types related bugs fixed. They are a bit more
flexible now.
And various minor compilation errors have been fixed. This includes
C/C++ compilation errors fixes, and some configure/Makefile tweaks.
--------------------------------------------------
Release Notes for Icarus Verilog Snapshot 20060618
--------------------------------------------------
Add support for system functions in continuous assignments.
Allow concatenations as arguments to inout ports. This comes with a
small variety of internal part select and concatenation bug fixes.
Fix some bugs in constant propagation through ternary expressions.
Fix broken subtraction if small constants in certain cases.
Fix a few datatype mismatch errors.
Make $readmem give warning when input is inadequate for requested
range.
Fix runtime of nand in continuous assignments.
Fix synchronous user defined primiteves to only follow edges.
Fix a runtime error in some thread delays processing.
Improve limited genvar expression handling.
Start a rework of expression elaboration. Make elaboration aware of
the expression context width when appropriate in order to better
handle expression width and padding.
Fix the make rules for parse.cc to reflect that they come from the
same source. Fix the autoconf.sh to configure the stub target.
Fix portability of the lexor source files on Windows systems. Get rid
of the isatty references.
Make a stub lround when the system version is missing.
--------------------------------------------------
* Release Notes for Snapshot 20060809
--------------------------------------------------
Some handling of real values is improved. Real valued literals are
handled in net contexts (continuous assignment, etc.). Also, modulus
of real operands now works. (This is an extension to the Verilog
standard.)
The power operator (**) now works.
Signed right shift works properly now.
The $sscanf and $fscanf are introduced, and work at least for basic
numeric values.
The release function now works to undo general force statements, and
not just contant force statements.
Delay constants up to 64 bits are supported. This at first doesn't
seem like an issue, but when precisions are mixed, it becomes
surprisingly easy to overflow 32bit delays.
The driver is reworked to pass many preprocessor details through a
temporary file instead of on the command line of a system(3)
call. This prevents confusing and incorrect shell processing of
complex strings passed as values to -D flags.
Various other little fixes.
|
|
A few new features have been added to allow proper simulation with
newer Xilinx UNISIM models. (They are starting to use Verilog 2001
features.) And also various bug fixes in this release.
-- Primitive and continuous assign delays can now be non-constant. This
needed some new run-time support, so vvp had a slight format change,
and certain new optimizations follow as a result.
-- Bug handling certain constant sub-expressions in concatenation
expressions. Also, allow concat expressions in constant contexts.
-- Support for wide divide expressions.
-- Fixes for stubborn compilers.
-- Fix bugs in padding of signed expressions.
-- More fixes for following the data types of expressions.
|
|
changes include:
Added support for the `default_nettype directine, including the
default net type of "none", which turns off implicit net declarations.
Signed /, % and >>> in nets should now work properly. Also, various
operators of all sorts applied to constants have been improved.
Ranges now work on localparams.
Added the system tasks $unsigned, $is_signed, $mti_random and
$mti-dist_uniform. See the make README.txt for a description of these
system functions. Also, flesh out the standard random number
generators to match the sequences generated by other compilers.
There is now an "sft" file that describes to the compiler the return
value of system functions. This allows user supplied system functions
to have interesting return types. See "SYSTEM FUNCTIO TABLE FILES" in
the iverilog man page. Include a sft file for the system functions,
and move the system functions over to that mechinism.
Fix the behavior of $fgets in tight fitting result buffers.
A variety of compilation environment fixes have been added. These
involve configure scripts and Makefiles.
And of course a variety of other bug fixes, and so on and so forth.
|
|
changes: bugfixes, VPI extensions
|
|
There was a couple of snapshots since february; besides bugfixes the
major highligths might be:
-handling of real values at various places
-support for library modules (esp cadence PLI1)
-better FPGA support (esp Virtex II)
-"vvp" interactive mode added
Also converted to buildlink2, and dependencies to libz, libbz2 and
readline added.
|
|
since the last packaged snapshot. Better language coverage, better
performance, improved synthesis, fixed bugs. Too much to list here.
|
|
many improvements and bug fixes since the last packaged snapshot including:
-added the $sizeof system function as a builtin
-In VPI, the simulator event callbacks now work
-Concatenation expressions in parameters were broken are broken
-added the vpiModule iterator to VPI scope handles
|
|
Release Notes for snapshot 20020317
The first difference in this snapshot from the 0.6 release is that vvm
is no longer compiled by default. If you want to compile vvm, you must
enable it at configure time (--enable-vvm) and rebuild from
scratch. Eventually, vvm will disappear from the release altogether.
The next major difference is new support for user defined
functions. It is new support, so it is bound to be buggy, but it
should be somewhat complete. The major problem has been solved, so all
that remains are bugs around the edges.
The vvp run-time scheduler has been changed slightly. The run time
behavior is getting increasingly precise and picky, as larger designs
are thrown at the compiler. The change introduced in this snapshot
fixes logic gates to not propagate zero-time pulses, and thus fixes
some weird bugs in large designs.
I've also added initial support for the Verilog 200x pragma comment,
which are (* *) pairs. For now, the compiler ignores them as
comments. This is what a compiler is supposed to do with anything that
is not specifically recognized.
Also, Tony (Anthony Bybell) has added LXT dump support. The LXT output
file is a waveform output format that is much more compact then VCD.
The gtkwave waveform viewer supports the LXT format, and should
operate a bit faster when viewing LXT files. For now, there are
separate system tasks for managing LXT output ($lxt_dumpvars, etc) but
eventually the dump format will be selectable by environment variable
or command line switch.
This snapshot also includes various random bug fixes and improved
error messages for incorrect code.
|
|
|
