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2004-10-03Libtool fix for PR pkg/26633, and other issues. Update libtool to 1.5.10tv1-1/+2
in the process. (More information on tech-pkg.) Bump PKGREVISION and BUILDLINK_DEPENDS of all packages using libtool and installing .la files. Bump PKGREVISION (only) of all packages depending directly on the above via a buildlink3 include.
2004-09-21update to verilog-current-20040915. Changes in this snapshot:dmcmahill2-5/+5
The big news is that module instance arrays now work. Gate and UDP instance arrays have worked for a while, but module instance arrays were more tricky because of the scope arrys they create. The issues have been dealt with, and module instance arrays are now supported. An interesting but subtle set of bugs in the evaluation of ternary expressions has been fixed. The problems expressed themselves when the condition expression was constant. Degenerate wait statements now work properly. The @* syntax apparently missed sensitivities in l-value expressions of assignment statements. This led to subtle bugs in carefully crafted bits of code. Verilog attributes are properly parsed in a few more contexts. Also, some specify syntax cases have been fixed. Some minor spelling and documentation errors have been fixed, along with assorted compiler warnings.
2004-09-02update to verilog-current-20040828dmcmahill3-7/+8
changes include: Added support for the `default_nettype directine, including the default net type of "none", which turns off implicit net declarations. Signed /, % and >>> in nets should now work properly. Also, various operators of all sorts applied to constants have been improved. Ranges now work on localparams. Added the system tasks $unsigned, $is_signed, $mti_random and $mti-dist_uniform. See the make README.txt for a description of these system functions. Also, flesh out the standard random number generators to match the sequences generated by other compilers. There is now an "sft" file that describes to the compiler the return value of system functions. This allows user supplied system functions to have interesting return types. See "SYSTEM FUNCTIO TABLE FILES" in the iverilog man page. Include a sft file for the system functions, and move the system functions over to that mechinism. Fix the behavior of $fgets in tight fitting result buffers. A variety of compilation environment fixes have been added. These involve configure scripts and Makefiles. And of course a variety of other bug fixes, and so on and so forth.
2004-06-07update to verilog-current-20040606dmcmahill2-5/+5
* Release Notes for Icarus Verilog Snapshot 20040606 Ports of primitives can bind by name as well as by position. Also support Verilog 2001 style port declarations for primitives. System function return types can now be specified by system function table files. System Function Table Files are described in the iverilog man page. Also include better system function return types in VPI. Non-blocking assign of real values to real variables now works. Properly handle nul strings ("") as 8bit values. This is a weirdness legacy of XL. Fix some synthesis problems for logical OR and logical AND. Bitwise OR and AND were fine. These fixes affected simulation as well. Handle wait statements with all sorts of constant values. These are sometimes weird, bug legal. Handle Negative value reals, and a few other bugs related to real numbers. Change internal use of identifiers to perm_strings for better performance. Functions returning unsupported types now generate error messages. Previously, they would quietly generate bad code. Infrastructure is also added to eventually support arbitrary function return types. Better compile-time support for Cygwin vs mingw32. The ipal target is removed from this source. (ipal is now an add-on package that is compiled seperately.)
2004-04-11No longer used.snj1-35/+0
2004-04-11Bah. Forgot to remove unnecessary includes.snj1-5/+1
2004-04-11Finish bl3ification.snj1-0/+22
2004-03-22add lex to the GNU_TOOLS list. Needed for SunOS and probably some others.dmcmahill1-2/+2
2004-03-12bl3ifydmcmahill1-14/+10
2004-03-02update to the 20040220 snapshotdrochner3-8/+16
changes: bugfixes, VPI extensions
2004-01-31s/seperate/separate/snj1-1/+1
2004-01-22replace deprecated USE_GMAKE with USE_GNU_TOOLS+=make.grant1-2/+2
2003-12-30Whitespace fixcjep1-2/+1
2003-08-25update to the 20030815 shapshotdrochner2-5/+5
changes are basically bugfixes, and improvements in the FPGA synthesis area
2003-07-17s/netbsd.org/NetBSD.org/grant1-2/+2
2003-07-14update to snapshot "20030705".drochner4-15/+18
There was a couple of snapshots since february; besides bugfixes the major highligths might be: -handling of real values at various places -support for library modules (esp cadence PLI1) -better FPGA support (esp Virtex II) -"vvp" interactive mode added Also converted to buildlink2, and dependencies to libz, libbz2 and readline added.
2003-05-06Drop trailing whitespace. Ok'ed by wiz.jmmv1-2/+2
2003-02-04update to verilog-current-20030202.dmcmahill3-25/+12
This is the first packaged (in pkgsrc) snapshot after the verilog-0.7 release. This snapshot adds preliminary support for real variables to the language to the features already found in verilog-0.7.
2002-11-10add buildlink2.mk file in preparation for some coming pkgs which need itdmcmahill1-0/+36
2002-10-22update to verilog-current-20021019dmcmahill3-31/+5
Release Notes for Icarus Verilog Snapshot 20021019 The synthesizer now detects asynchronous set/reset inputs to DFF devices. The fpga and vvp code generators have been updated to support these signals. The vvp code generator also gained some register management code that improves the thread register usage. This redoces code size for certain common cases, and thus improves simulation performance. The requirements on `ifdef and related compiler directives has been relaxed, to correspond to more common behavior. The parameter range support crashed if the range expressions had parameters in them. This is fixed, and some signed-ness bugs fixed along with it. Rearrange some of the configure script tests to assure better compatibility accross platforms.
2002-10-17fix the iverilog-vpi shell script (bash-isms)dmcmahill3-2/+28
2002-10-13update to verilog-current-20020921 snapshot. Many improvemnts in thedmcmahill2-5/+5
synthesis code and bug fixes in the simulation code since the last packaged snapshot.
2002-08-29update to verilog-current-20020828dmcmahill2-5/+5
Release Notes for Snapshot 20020828 This snapshot adds support for parameter and localparam bit ranges. This is a IEEE1364-2001 feature, although some -1995 compilers have supported it in the past. Fixed a *nasty* and slippery bug with the evaluation of bit select of nets. (Bit select of variables was unaffected.) The symptoms did not clearly point to the problem, so bugs related to it were often mis- reported. Gate delays were lost when constants were propagated to their inputs. This is fixed for the known broken cases. Also, mux output delays have been fixed. Also, release statements that apply to elided nets are turned into no-ops. The r-values of non-blocking assignments are now precalculated at compile time, if possible, as is done with blocking assignments. This speeds up constant propagation, and is more thorough. Also optimize subtraction of small constants from vectors, with the new %subi instruction in vvp. This saves some in code size and thread footprint. Handling of x in r-value bit selects and memory word selects did the wrong thing. Now they do the right thing. Also, x in the selector of ?: ternary operators does the right (and complicated) thing now. In the process, a fork-join code generator bug was fixed. Several bugs with time formatting have been fixed. Temporaries in sequential blocks are detected by the synthesizer, and converted into wires when needed. This expands support for combinational logic synthesis.
2002-08-24update to verilog-current-20020817. Many many changes and bug fixesdmcmahill3-8/+10
since the last packaged snapshot. Better language coverage, better performance, improved synthesis, fixed bugs. Too much to list here.
2002-05-07update to verilog-current-20020505dmcmahill4-11/+25
many improvements and bug fixes since the last packaged snapshot including: -added the $sizeof system function as a builtin -In VPI, the simulator event callbacks now work -Concatenation expressions in parameters were broken are broken -added the vpiModule iterator to VPI scope handles
2002-03-28update to verilog-current-20020317dmcmahill3-15/+8
Release Notes for snapshot 20020317 The first difference in this snapshot from the 0.6 release is that vvm is no longer compiled by default. If you want to compile vvm, you must enable it at configure time (--enable-vvm) and rebuild from scratch. Eventually, vvm will disappear from the release altogether. The next major difference is new support for user defined functions. It is new support, so it is bound to be buggy, but it should be somewhat complete. The major problem has been solved, so all that remains are bugs around the edges. The vvp run-time scheduler has been changed slightly. The run time behavior is getting increasingly precise and picky, as larger designs are thrown at the compiler. The change introduced in this snapshot fixes logic gates to not propagate zero-time pulses, and thus fixes some weird bugs in large designs. I've also added initial support for the Verilog 200x pragma comment, which are (* *) pairs. For now, the compiler ignores them as comments. This is what a compiler is supposed to do with anything that is not specifically recognized. Also, Tony (Anthony Bybell) has added LXT dump support. The LXT output file is a waveform output format that is much more compact then VCD. The gtkwave waveform viewer supports the LXT format, and should operate a bit faster when viewing LXT files. For now, there are separate system tasks for managing LXT output ($lxt_dumpvars, etc) but eventually the dump format will be selectable by environment variable or command line switch. This snapshot also includes various random bug fixes and improved error messages for incorrect code.
2002-01-16update to verilog-current-20020112dmcmahill2-6/+12
many many changes since the last packaged snapshot. A brief sampling of the changes (which include many bug fixes and enhancements) is: A variety of little problems with $display format strings have been fixed. The % operand should now simulate properly. Also, the * operator is a little bit more optimized, and works in constant expressions. Several bugs in strength modeling have been fixed. This includes drive strengths on continuous assignments, which in the past generated code without the strengths. Also, vvp gained some missing support for constants with strength. I think that strength modeling is now complete. vpi_get_vlog_info support has been added to the vvp run-time. This is a PLI function that allows access to run-time command flags. Also, vpi access to root modules now works properly.
2001-12-15update to verilog-current-20011209 snapshot.dmcmahill2-6/+6
Many changes since the last packaged snapshot. A sampling of these are: Support for hierarchical names has been largely rewritten. The major consequence of this is that escaped names now have much better support. By now, most any combination of escaped and hierarchical name should work properly, for nets, parameters, and anything else. Output delays for primitive gates, including user defined primitivies, should now work properly. Delays on nets still do not work, although the parser now parses them and prints a "sorry" message. Bugs in support for division(/) and modulus (%) have been fixed. Bugs in l-values of synthesized DFF devices have been fixed. These bugs were related to part selects of vectors in l-values. A few XNF code generator bugs and limitations were fixed. And as usual, a variety of miscellaneous bugs have been fixed in this snapshot. The bit size of the results of some unary redunction operators is now properly handled. Also, similar problems with logical functions have been fixed. force/release now works for variables, though not yet for nets. Assign/deassign already work. many other bugfixes
2001-11-01Move pkg/ files into package's toplevel directoryzuntum2-1/+1
2001-10-24update to verilog-current-20011020.dmcmahill3-11/+16
changes since last snapshot include: - addition of a fpga target for synthesis. outputs edif, optimized for xilinx virtex parts. - fixed bug with synthesis of != - fixed bug in hex constant parsing - fixed vvp bug with subtracting very wide words - much improved VCD output - many other bug fixes and robustness improvements.
2001-09-27Mechanical changes to 375 files to change dependency patterns of the formjlam1-2/+2
foo-* to foo-[0-9]*. This is to cause the dependencies to match only the packages whose base package name is "foo", and not those named "foo-bar". A concrete example is p5-Net-* matching p5-Net-DNS as well as p5-Net. Also change dependency examples in Packages.txt to reflect this.
2001-07-03update to 20010630 snapshot.dmcmahill5-371/+9
changes are: ----------- RELEASE NOTE FOR ICARUS VERILOG 20010630 I've done some cleanup of the mingw port of Icarus Verilog. I've also added instructions for how to build Icarus Verilog under mingw. I'm working on making that the preferred way to support Windows, and when I make the 0.5 release I will make Windows binaries this way. Anyhow, feedback on the build instructions and the build results using the instructions in mingw.txt are welcome. I've make "vvp" the default target type. The older vvm behavior is available with the "-tvvm" flag to iverilog, but I would rather be told about (and fix) bugs in the vvp code generator and run time. I've added support for the (unsigned) right shift operator. The left shift has been working for a while now, but right shift somehow slipped through the cracks. The shift operators still don't quite work in structural contexts, but they should show up sometime next week. I've finally got VCD output working properly with vvp. It may even be better then with vvm, although some internal symbols are still generated. A few odd bugs have been fixed, including a code generation error for xnf, and error checking of user defined function parameters.
2001-06-11CPPFLAGS is now passed to MAKE_ENV and CONFIGURE_ENV by bsd.pkg.mk, sojlam1-2/+1
adapt by moving CPPFLAGS settings to top-level, and removing explicit inclusion of CPPFLAGS into MAKE_ENV and CONFIGURE_ENV.
2001-05-21update to verilog-current-20010520.dmcmahill5-23/+382
many changes since the last snapshot. Mostly they involve expanded VVP support. The VVP target now passes >200 of the tests from the test suite. While not as complete as the VVM target, VVP is getting closer and its _much_ _much_ faster.
2001-04-28update missing distinfo file from update. Thanks to Thomas Klausnerdmcmahill1-3/+3
for catching this one.
2001-04-28update to verilog-current-20010422dmcmahill1-3/+3
Changes since the last packaged snapshot from the authors announcements: Icarus Verilog snapshot 20010422 -------------------------------- I've integrated a bunch of UDP patches from Stephan Boettcher. These go to the core of ivl, so if you use Icarus Verilog with UDPs, you might want to give this a test for us. Stephan has also added some ivl_target support for UDP devices. This is a prerequisite to vvp support for UDP devices. Some of you have been beating me over the head about disable, so the vvp target now supports disable. It only works in certain very constrained situations, but the idea is there and the more common cases are simply a matter of getting around to them. I actually could use more examples of the use of disable for the test suite. In the process, I have settled on the interaction of threads and scopes, and changed the %fork syntax to match. See the README.txt and opcodes.txt file for details. The implementation of %end and %join simplified in the process. The vvp-tgt code generator supports a few more gate types. New gate types are pretty easy to add, it's just boring grunt work. That's why they've been popping up slowly. I've also got certain behavioral shifts working. Only constant shifts, so far, but this covers a pretty large percentage of the real world uses of shift, I think. I fixed a few specify block parse problems, so it should ignore even more complex specify blocks now:-) One of these days I really will properly support specify blocks. PROGRESS I was hoping to get vvp up to a similar level as vvm by the end of April, but that doesn't look like it's going to happen. I'm up to 182 tests passed, compared to 318 of Icarus Verilog/vvm, so I have a ways to go yet. I see no real point to making a release until I get up to 300 or so tests passed. That is the goal for 0.5 release. But of course if vvp is enough for you, then it is soooo much faster then vvm. Icarus Verilog 20010415 Snapshot -------------------------------- As with all the most recent snapshots, this is almost entirely progress with the vvp code generator and simulation engine. I'm up to 159 tests passed in the test suite, so I'm getting there. But there's still plenty to go. I also fixed what appeared to be a minor problem with elaboration of ?: expressions in continuous assignments. The code was actually fine, it was a spurious assert. This fix affects vvm as well. Icarus Verilog/vvp now support <= statemements with internal delays. That is, "foo <= #10 bar;" should work properly, and there are tests in the suite that prove it. This is a pretty common syntax, so this should help a lot of folks. I also fixed a bug in the code generator that would cause it to put a constant bit as a destination for the bitwise boolean operators. This caused run-time asserts. The event or support in vvp has been extended to now support arbitrary width, so now you can for example wit for any changes in a 32bit reg. This handles most of the likely cases, so @ statements should now be pretty generally functional. The handling of run-time threads has been revamped in preparation for support of the disable statement. It also plugs a memory leak where fork/join and task/function calls are invoked. And this version should also clean up all those tiny initial foo=bar threads that all programs seem to have. Threads that are done are now freed, along with their memory, hopefully reducing the runtime memory footprint. That's pretty much it this time 'round. Working with threads took some time, so the progress isn't as flashy as it sometimes is. There is still lots to do with vvp before 0.5, but I would appreciate any feedback you can offer. It's complete enough already that I'm able to accept bug reports on it, even if it turns out to be a "not supported yet" type of thing. At this point, I'd be curious to know what hangups are preventing its regular use.
2001-04-19Move to sha1 digests, and add distfile sizes.agc1-1/+2
2001-04-17+ move the distfile digest/checksum value from files/md5 to distinfoagc3-7/+5
+ move the patch digest/checksum values from files/patch-sum to distinfo
2001-04-14update verilog-current to 20010407dmcmahill9-84/+16
changes since last snapshot are (from the authors email) verilog-20010407 -------------------- Still more progress on the new VVP simulation engine: As with last week, this snapshot includes a lot of work on the ivl_target API in support of code generation for vvp. Also, the vvp execution engine has progressed some. In fact, vvp has grown up to understand signed vectors and some signed expressions. The signed vectors are mostly for VPI use, the signed comparison instructions actually do signed work. Case comparisons are new, along with %and and %or instructions, and %nor/r for reduction. I also added a few new gate types to the .functor support. A bug in the propagation of values by %set instructions has been fixed. Specifically, the %set instruction not only sets the value of the .var that it references, but also executes the propagation events that result. This fixed some event ordering bugs. Some VPI support needed by system.vpi is added to vvp to allow it to properly handle signed signals, decimal values, and a few other details. $display should work much better then it did last week. Back in the vvp.tgt code generator, lots of new stuff is happening. Several of the bitwise binary operators have been added, as well as more comparison operators. This includes handling of signed expressions. This also implies that vvp.tgt generates the proper .net vs .net/s and .var vs .var/s statements. User defined functions and tasks are now working. In fact, the vvp target probably handles more functions (in behavioral code) then the vvm engine. I've received several bug reports about user defined functions with loops, that don't work under vvm. These should work with vvp. Non-blocking assignments now work, too. All forms of case/casex/casez are supported by the code generator, and use the proper compare instructions. Forever, Repeat and While loops also work now. A few bugs in event handling, and all the edge types (including behavioral triggers) should work with limitations. Event or is still in the works, and any-edge of large vectors (>4 bits) does not work. *Whew!* As you can see, a *lot* of stuff is happening. I'm up to passing 110+ tests in the regression test suite (Icarus Verilog/vvm passes 318 tests) so the changes are actually making things work. Test and be merry! verilog-20010331 -------------------- More and more progress on VVP. More and more snapshots. A lot of work has been done to the ivl_target loadable target API. This API is growing to support the also growing tgt-vvp target. I've added support for case statements, event triggers fork blocks. Of course this also means that the tgt-vvp code generator and the vvp simulator now support constructs including case, events, and parallel blocks. I've also fixed up the driver to properly report errors that tgt-vvp detect. This makes the test suite regression script work a lot better. I'm up to more then 70 tests in the test suite passing. I'm finding that writing the code generator for vvp assembly is a *lot* easier then writing a code generator for C++/vvm. Fortunately, the vvp assembler is pretty fast. At any rate, the vvp simulation engine is starting to show signs of being useful. It still does not cover nearly as much of Verilog as vvm, but what it does cover is so much faster that it may be worth your while to try it out. And more eyes looking at it can only be a good thing.
2001-04-11Use wildcards in CONFLICTS.wennmach1-2/+2
2001-03-31update to verilog-current-20010324. Changes since the last version fromdmcmahill10-18/+88
the authors announcement are: There are a few bugs in the main compiler that are fixed. There has also been an extension to the $fopen that adds support for opening files for reading. The $fgetc has been added to take advantage of this. This was done on the VPI side, although a slight extension to the mcd functions was created. The real news is the vvp simulation engine. I've added the tgt-vvp code generator source and the vvp assembler/simulator, and the combination actually produces the occasional working program. And it makes them very quickly. So far as I can tell now, I am going to be very pleased with the final outcome when this work is complete. However, it is not at all ready to use. This snapshot is mostly to give a preview of things to come to a wider audience. HOW VVP WORKS If you are accustomed to the existing vvm behavior, you remember that the vvm simulator works by generating C++ and feeding that to the g++ compiler. Many of you are painfully aware of that. VVP does *not* work like that. Instead of generating C++, the generator emits assembly language for an abstract simulator processor. The processor that the assembly targets doesn't really exist, but the vvp program, included in this Icarus Verilog snapshot, assembles the code to data structures in memory, then efficiently emulates the abstract processor. So the simulation of a program via vvp works by first compiling the Verilog to vvp assembly. The vvp.tgt modules generates the code, and is envoked when you use the ``-tvvp'' switch to iverilog. The vvp assembly file so created is then passed to the vvp program to be assembled and executed. There is a single vvp input file that is the design to simulate. The vvp assembler is designed to execute the design efficiently. HOW TO LEARN MORE The ivl_target.h header file describes the loadable target API that the vvp code generator uses to gain access to the design. Then the tgt-vvp directory contains the implementation of the vvp code generator. The vvp directory contains the implementation of the assembler/simulator that runs the compiled design. The README.txt file describes how the vvp program works in general, and points to other txt files. There are a variety of other .txt files in the vvp directory that describe how the major components of the vvp program work.
2001-03-27Change BUILD_DEPENDS semantics:hubertf1-3/+3
first component is now a package name+version/pattern, no more executable/patchname/whatnot. While there, introduce BUILD_USES_MSGFMT as shorthand to pull in devel/gettext unless /usr/bin/msgfmt exists (i.e. on post-1.5 -current). Patch by Alistair Crooks <agc@netbsd.org>
2001-02-16Update to new COMMENT style: COMMENT var in Makefile instead of pkg/COMMENT.wiz2-2/+2
2001-01-14update to verilog-current-20010113dmcmahill2-5/+5
bug fixes and signed support (yay!). detailed changes since last packaged snapshot from the authors announcements: Icarus Verilog snapshot 20010113 -------------------------------- We're getting close to release candidates. Maybe another snapshot, then I start with making 0.4 release candidates. So lets get this tested so that I can move forward! This snapshot largely fixes a whole bunch of bugs. I'm working feverishly to catch up to the reported bugs, but they are coming in about as fast as I can resolve them. (Not that I'm complaining, mind you. These PRs are really helping me make it better.) But that means I'm going to just concentrate on getting as many PRs done as I can before the release. The syntax of functions and tasks has been expanded to allow parameters. This is not a common thing to do, but someone puts parameters if functions The syntax of functions and tasks has been expanded to allow parameters. This is not a common thing to do, but someone puts parameters if functions so I had a PR to fix:-) Also I caught a problem with executing functions that take no input parameters. In fact, a bunch of function related bugs were fixed. I lost track of em all. Ports of tasks weren't elaborated properly. I fixed this and a few related problems so most legal l-values should work as task port expressions now. Memories within tasks should also work properly now. Speaking of ports, I now report errors when there is a port direction for module ports that don't exist. In fact, there are a whole bunch of cases where I've added required error messages. The %d format of display strings now displays signed negative values as negative values instead of the unsigned equivalent. This goes along with the other signed arithmetic features from the -2000 standard that are now supported. I fixed up the Makefiles (thanks to a contribution) to support build using the VPATH capabilities of the makefile. You should be able to compile for multiple targets now from a shared source directory. Icarus Verilog snapshot 20010106 -------------------------------- I'm just managing to barely keep up with the bug reports arriving in the bug tracking system. I'm pleased with the success of the ivl-bugs robot. These bug reports have allowed me to better manage and record progress. Keep those bug reports coming! I've added support for arrays of integer and time variables, as well as the Verilog 2000 initialization syntax for these types. I have also made some internal changes to integer support. Integers are now just a shorthand for ``reg signed [31:0]'' and signed variable support has made some internal changes to integer support. Integers are now just a shorthand for ``reg signed [31:0]'' and signed variable support has been generalized. This makes it easier on the code generators, as they do not need to know that a variable was a integer, a time, a foo or a bar. I few constant propagation errors have been fixed. Continuous assignments of constants to nets should behave correctly now. Many people noticed lack of expression support for parameters. In fact, the problem was a lack of support for a bunch of specific operators. I've added many operators. This has the side effect of improving constant propagation as well, in some cases finding more dead code to eliminate. This also affected expressions that were index expressions of memories and vector declarations. The / operator in continuous assignment expressions is fixed. There were a few size related issue here that are now fixed. I've added to the i3331364-notes.txt file a clarification of my position on parse of repeat statements. This position is compatible with XL behavior. Passing parameters to user defined functions in behavioral code was pretty darn broken. I managed to fix this. You can tell that not many people use user defined functions:-) (It doesn't help that Icarus Verilog is picky about them.) For vvm, I've put some effort into optimizing the compile time of programs by reducing the size of the output code. I've reduced redundancies some, and used loops to handle vectors where possible. A few bugs related to $dumpvars were cleaned up. Function scopes work.
2000-12-19update verilog-current to 20001216.dmcmahill6-13/+30
Changes since the last packaged snapshot are (from the authors announcements): Icarus Verilog snapshot 20001216 -------------------------------- This is the last snapshot before the holidays, so I hope it has your favorite present in it. A lot of PR#s have been dealt with, and for a brief moment I felt like I was getting ahead of the pending list:-) I've added support for non-integer times, at least in a few contexts. The `timescale directives should interact properly with the decimal point in delays, causing more accurate timing simulations. This should make vendor-supplied libraries work much better. I've added support for signed reg variables. Signed expressions should now generally do the right thing, but this feature needs much more testing, and many more tests in the test suite. However, I do know that signed comparisons should work properly. Bug reports for problems with signed arithmetic are encouraged. Many people have been having troubles with Cygwin compilation. The problem was with the latest version of binutils. Venkat came up with a solution that works with old and new binutils, so you can now compile with the very latest cygwin software. This should make things a lot easier for a lot of people. I've made initial steps toward an HP/UX port. The configure script should detect the right dl library to use, and the t-dll target should be able to load loadable targets. I am looking for a volunteer to take responsibility for the HP/UX port as I have no suitable machines. Said person should be able to compile Icarus Verilog, manage HP/UX specific portability issues, and be able to make precompiled packages when the stable release is out. I'm still looking for a similar volunteer for FreeBSD/{alpha,i386}. Some more progress was made on support for PALs. I'm close to choosing macrocell modes and configuring fuses. Won't be long now, folks. Icarus Verilog snapshot 20001129 -------------------------------- few more constant propagation improvements this time, most notably XOR an XNOR are now fairly complete. These are interesting as they are generated by comparison operators so show up pretty often. And it is common to compare numbers to constants. Thus, there are lots of oppor- tunities for gate elimination! Synthesis of unary ! now works. Unary ~| (reduction nor) should also be in good shape now, as should binary || (logical or). Synthesis of binary && is still a little shaky. Go ahead and file reports if you trip on it. Binary != was broken with XNF synthesis, so that is also fixed, along with a few cases of mangled XNF output. And there were also a few bugs related to the CE of inferred DFFs, that didn't get connected. A *big* problem with synthesis occurred with non-blocking assignment. Icarus Verilog simply failed to synthesize the r-value of the assignment and all kinds of bad things happened. I fixed this, it's better now. Whew! Lots of XNF synthesis bugs fixed! This is what happens when users take the time to submit good bug reports. There are also some bugs related to dead signal elimination that causes Icarus Verilog to crash in some synthesis cases. These have been fixed up so far as I know. I have slightly improved root module detection of iverilog. If there is only one module in a source file, it is pretty obvious that it is the root module, even if it has ports. This is a common case for XNF synthesis (especially when making small macros with Icarus Verilog) and should save some typing and confusion.
2000-11-24rest of upgrade to verilog-current-20001119dmcmahill2-3/+4
don't know what happened the first try.
2000-11-24update to verilog-current-20001119dmcmahill1-3/+3
changes since the last packaged version (from the authors announcements): Icarus Verilog snapshot 20001119 -------------------------------- The big change here (code wise) is improved and corrected constant propagation. I was missing OR, NOR, NAND and XOR propagations, and got some of the AND calculations wrong. This fixes this shortcoming and in some cases this actually may speed up your compile a tiny bit. Some more dangling signals are also eliminated. supply nets are now working (PR#17). They also will trigger constant propagation (as they have constant values) in certain cases. Those of you doing cygwin compiles have trouble compiling parse.cc. I've put into the cygwin.txt some slightly better instructions for dealing with this situation, when it comes up. I've also added missing symbols to ivl.def, so that tgt-stub properly links. Icarus Verilog snapshot 20001112 -------------------------------- This snapshot includes support for MOS et al devices as contributed by Tim Leight. It appears to actually work as advertised, and I also have from him a collection of tests that I'll be adding to the test suite as soon as I get copyright information from him. So if you have been dreaming of simulating MOS devices with Icarus Verilog, give this a try. This update also fixed PR#27. I've also cleared up a few bugs related to unconnected module ports. Module port syntax is pretty byzantine, as PR#38 shows. The loadable target API has gained access to flip-flops. This is required for PLD code generation to work. I think the ivl_target API now supports the minimum devices needed to generate PLD files, and I'm on to the task of getting ancillary PAL support working. Icarus Verilog snapshot 20001104 -------------------------------- Yes, I've managed to find the right bits to get Icarus Verilog to compile on RedHat 7.0, and this snapshot includes those fixes. It took some back- and-forth with tech support at RedHat to get it going. I've also fixed up make check so that it works in general. If you use "make check" after building, the makefile will run the examples/hello.vl program through the local parts to make sure they minimally work. I've added support for the "time" data time and more complete support for the $time system function. These should work properly in all cases now, so cases of not working are worthy of a bug report. I've also integrated a re-implementation of sequential UDPs from Stephan Boettcher, so I would appreciate it if all you folks using primitives give this a fresh test. (It should be an improvement.) This is a relatively small message, which doesn't reflect the complexity of the changes. The "time" support in particular caused a lot of threads to be pulled. Also, I've been doing some PLD stuff on the side, so I've been busy. I've also knocked of PR#11, 14, 33, 34, 39 and a few other bugs.
2000-10-27update to 20001021 snapshot of verilog-currentdmcmahill6-22/+13
from the authors announcement: ----------------------------- The loadable target module API is starting to take shape. That is the major thrust nowadays with Icarus Verilog, after all, so progress is being made here. The biggest change is in fact a philosophy change. The target module now needs only a single symbol -- target_design -- to receive the whole design. The target module can from there and using the API access the entire design randomly. So if you wanted to implement a graphical browser, you could:-) I've added support for the l-values of procedural assignments, and also back pointers to objects that reference ivl_nexus_t objects. This closes the loop so that there should be no dead-ends in the design. I've clarified and expanded the descriptions in the ivl_target.h header file. There should be just about enough documentation to properly used all the various types. (Have any of you tried to write GIMP plug-ins? Have you looked at the libgimp header files? Have you seen any comments there?-( I won't ever sink to that level, I hope.) I've also imtegrated updates to the Cygwin32 port to support loadable targets under Cygwin32. After much struggling, Venkat managed to discover the secret magic needed to get load time symbol binding to work. Hopefully I didn't break it too bad when I changed the API again. (I think it is still fine.)
2000-08-06update to verilog-current-20000805. Changes since the last packaged snapshotdmcmahill7-42/+14
are (from the authors announcements): -------------------------------- Icarus Verilog snapshot 20000721 -------------------------------- (first snapshot after the 0.3 release) This snapshot adds no new features or language support, but is working towards more precise interpretation of scheduling and value propagation details. The first thing I've done is redesign the internal Link structure that is used to connect the internal netlist together. There are some aspects of the nexos of a set of links that were carried by the Link class or by external functions. These have been moved to the new Nexus class and linking and structure has improved because of it. This has led me to modify the handing of signal initial values. In practice, the time-0 value of a net is a property of the nexus instead of the objects that are connected together, so I have implemented it so, and in the process fixed a bunch of initial value problems. One new feature that is added is support for non-constant delay expressions. Now, you can even have something like ``#($random%256) <statement>'' and expect it to do what you think. (So now the telephone example in James Lee's "Verilog Qickstart" actually works!) I've added some missing support for various operators in constant expressions. I've also added some more of the friends of $random for those folks who do stochastic modeling. Constant propagation carries some new bug fixes, and some new smarts. It is for example able to detect a mux with a constant 'bz input and replace it with bufif devices, and other clevernesses with logic reduction. -------------------------------- Icarus Verilog snapshot 20000729 -------------------------------- Like I said, the `timescale compiler directive now more or less works. You can now specify timescale for modules, and the compiler will figure out a global design resolution and scale your time values to match. The VCD dumps should reflect the chosen resolution automatically. Floating point notation is not yet supported, we'll see if that turns out to be a problem. A problem with `timescale support is that the compiler will allow unitless modules. This can happen if you have `timescale late in the source file. The default unit is the not-very-intuitive 1s. Frankly, I don't like the `timescale semantics for this sort of reason, but its an accepted standard, so I'm stuck with it. I've also added support for min:typ:max expressions. The compiler chooses one of the three expressions at compile time, based on a compile time switch. You can ask for min typ or max values via the "-Tmin" etc. switch to the iverilog command. If you do not specify a switch, the compiler will choose the typ values but print warnings. The -Ttyp switch will suppress the warnings. I have fixed yet more net initialization bugs. These are getting pretty subtle, now, so you should have a hard time tickling any remaining errors here. I've also fixed a nasty and subtle bug in event expression support. This bug only happened when the design had many event expressions with many conjunctions. Although they are not ready for use, I have made some forward progress with disable statements. I now at least elaborate them, so now I just need to figure out how to make the run-time work out. That's the hard part, I'm afraid. -------------------------------- Icarus Verilog snapshot 20000805 -------------------------------- I've finally dealt with a problem that's been nagging at me for a while. Until now, it has been possible that excessively clever hierarchical references into and out of task scopes could confound symbol lookup. I think I finally put that to rest, and in the process reorganized the netlist format for holding task definitions. It should no longer be possible to confuse name binding in Icarus Verilog. Found and fixed a silly bug in elaborating e?a:'bz and e?'bz:a expressions into bufifN devices. I got the sense of the enable wrong in one of the cases. All fixed (and the test suite updated to catch this silly mistake:-) tri0 and tri1 nets should now work properly. These are mostly a run- time issue which I solved using resolution functions. This is actually a technique that I borrowed from VHDL. For those of you doing XNF synthesis, I fixed up my FF/RAM detector to allow <= assignments in always blocks. This is in fact the preferred way to describe DFFs as <= more accurately simulates their RTL nature. Also found and fixed a few DOS \r\n line end issues in the lexical ana- lyser and the preprocessor. We sometimes forget how tricky these line- end problems can be, and compiler directives are the most susceptible. This problem most likely occurs when you transport files from a DOS environment. (The MAC folks haven't complained much, so either I got it right for them, or Kato took care of the problems for me:-)
2000-06-12compile with -fPIC instead of -fpic. Makes things work right on sparc.dmcmahill2-1/+13