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changes since last packaged snapshot are (from the authors announcements):
Icarus Verilog 20000527 Snapshot
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It's snapshot time!
<ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20000527.tar.gz>
This snapshot doesn't add any new features, but fixes a few bugs. I've
taken care of a bunch of bug reports with an eye towards getting this
polished up for a 0.3 stable release.
I fixed some problems with elaborating the condition expression of a
ternary operator. This was a long-standing bug that only happened in
structural (i.e. continuous assignment) situations.
I've also done some merging of event expressions. The netlist format makes
NetEvProbe and NetEvent objects for event expressions, and it was making
more then were needed. I've done some merging, though I have some more
things I can do on this front. I'll be working on it for the next snapshot.
I found a whole bunch of bugs with parsing expression lists, for example
module port expressions. The result is actually a smaller parser:-) So
module port expressions should be parsed and elaborated correctly, now.
In the vvm code generator, I've found some room to optimize the generated
code. I detect duplicate initialization of a nexus, and prevent the
excess code being generating. In one slightly degenerate example sent to
me, this change reduced the generated C++ by more then 6 times. I was
pretty amazed.
I've also slightly optimized the special case of behavioral assignments
from simple signal expressions. This removed a few lines of generated
code per assignment. This sort of thing helps compile time performance.
Icarus Verilog 20000512 Snapshot
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This is mostly a bug fix snapshot. No new features here, but I'm starting
to buff it up shiny for an upcoming 0.3 release. It looks like I'll be
starting to do release candidates soon, so test this snapshot hard, folks!
<ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20000519.tar.gz>
I re-implemented flip-flop and RAM synthesis, the new technique should
allow me to make much more complete synthesis. It's still not the nifty
full-scale synthesis I hope to do some day, but it should catch some of
the bigger synthesis problems.
I've also added to XNF synthesis the ability to detect start-up initial
values for flip-flip devices. This causes it to generate INIT= properties
for the devices as appropriate.
I've improved the VVM code generated by the t-vvm code generator. I've
managed to reduce the size of the code generated for some larger models
by 30%, and I should have improved run-time performance in the process.
This should help.
I've also found (thanks to bug reports) and fixed some module port issues.
I bet you can't dream up legal port binding that Icarus Verilog can't
handle:-) This issue should be taken care of.
VPI now includes the ability to set registers. I needed this to implement
a PNG image I/O module. I'm still working on that, I'll distribute it
separately when it is in better shape.
Various other bug fixes in iverilog and elsewhere. Several bug fixes
in the VVM runtime, including some support for the % operator.
I've done some updates to documentation to reflect some of the changes
since 0.2, so you can take a look at that too.
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changes from the last packaged snapshot (from the authors announcement):
---------------Icarus Verilog 20000506 Snapshot------------------
A lot of internal reworking has been done on this, so there might be
problems with things like symbol binding. But I think this is much better
then the last snapshot. I am once again starting to think about a
stable release. I'll shoot for the end of May, so if there is anything
you want to see in that release, start pestering me.
The big job has been a rewrite of the symbol table that holds signals.
The previous elaboration and lookup code for signals/memories did not
work properly when hierarchical names were used in the context of tasks
and functions. Also, the old table kept all the signals is a single
lookup table that failed to take advantage of knowledge of the current
scope.
All that is changed. signals are now elaborated after parameters and
before processes, so all hierarchical accesses should work properly now,
no matter how contorted. I've also fixed some bugs with function/task
parameter passing.
I've also added some infrastructure for supporting system functions, and
I've added an implementation of the $random system function. This currently
uses the native random(3) C library function, but once I get access to the
standardized algorithm, I'll implement that.
There are also a few fixes to elaboration of ternary operators. They were
a bit touchy about result bit widths.
A few preprocessor bugs have been fixed, especially related to the
`ifdef/`endif tokens. People are all the sudden starting to use the
Icarus Verilog preprocessor, so some long-standing bugs have been caught.
The iverilog command had a few path problems fixed, and the remaining
necessary switches have been added. I really encourage people to start
using iverilog in place of verilog. The test suite now uses iverilog to
run the compiler, so should you. There is a man page.
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its more obvious of the difference.
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The many bug fixes and changes since the last packaged snapshot
are (from the authors announcements):
Icarus Verilog 20000428 Snapshot
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This one clears up some pretty nasty and subtle bugs. If you've been
sending me bug reports, you're probably turning blue holding your breath
in anticipation of this snapshot. Breath in, Breath out.
Hooray, both force and release work properly. I'm happy about that,
release worked out a bit easier then I expected. These should be useful
to test bench designers.
The big news this past week, however, has been bug fixes. Lots of bug
fixes. I got lots of bug reports and I killed pretty nearly all of
them. There were lots of nasty icky problems with passing parameters
to/from tasks, especially when memory words were involved. I fixed up
a whole bunch of these, and now parameter passing should work pretty
will, modulus the few remaining bugs I'm not seeing yet.
The iverilog command is in better shape now, and I encourage people
to use it in place of the older "verilog" driver script. There is a
man page for iverilog, and it supports all the switches needed to do
simulation and synthesis. I would like people to start getting this
driver well tested and the bugs worked out, because it is going to be
the main driver come the next stable release.
Some neat new XNF features are happening. I synthesize identity compare
in XNF, and a few other missing operators. But the really neato part is
that I've taught Icarus Verilog to generate PIN records for module
ports, so that you can make XNF macros out of Verilog source. If you
elaborate a module that has ports, the XNF code generator will automatically
generate the necessary symbols so that external XNF tools can link the
generated output into larger designs. I've compared the XNF files from
Icarus Verilog with those generated by Abel, and they appear the same
to my eyes.
Icarus Verilog 20000421 Snapshot
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Bunches of bug fixes, and a few new features come with this snapshot.
This snapshot makes headway in both simulation and synthesis. I'm
also starting to make a big dent in my todo list for the 0.3 release.
The bunches of little bug fixes in this snapshot are a direct result of
bunches of bug reports this past week that I was able to deal with. If
you've been reporting bugs, this may contain your fix.
I redesigned the process implementation in the vvm backend, so the generated
code is a bit cleaner, and threads are lighter weight. And while I was at
it, fork/join now should work properly. I know there were a bunch of you
out there asking for this, so here it is.
I've incorporated into this release improved runtime support for integer
multiplication, it should now work now matter how incredibly enormous
you make the operands. Thanks to Chris Lattner for contributing the generic
multiply.
I've improved synthesis somewhat, there were some expressions in some
contexts that were not getting synthesized by the -Fsynth functor. This
is fixed, and I'm also starting to add some XNF specific optimizations
into the -Fxnfio functor. I do sensible things with identity compare,
for example.
I've added the program ``iverilog'' to be a new driver program written
in C instead of as a shell script. This driver supports the -tnull,
-txnf and -tvvm targets, as well as the -E flag that causes only the
preprocessor to be run. This should be interesting to those of you who
are looking for a working preprocessor. I'm still working on the -D and
the -I flags, but I expect this program to replace the verilog.sh script
before the 0.3 release.
Icarus Verilog 20000414 Snapshot
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All event handling is now complete. Yet another subject is behind me, and
on I go. By complete, I mean that named events, edge triggers, wait, and
lists of events all work. This took a little longer then I expected, so
some of the other things I wanted to work on had to wait.
As a side effect of event and thread scheduling work, I changed the way
that threads are generated in vvm. The result is that threads should be
a little faster at run time, and a lot faster at compile time. A *LOT*
faster at compile time. (Apparently, Verilog XL is still considerably
faster, but hey, I'm working on it.)
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changes since the last packaged snapshot include:
Icarus Verilog 20000326 Snapshot:
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The VVM backend rewrite continues. More templates are gone, and the
bit functions have been pretty much rewritten. The vvm library now handles
bit values with strengths, and most of the devices to the right things
with those strengths.
The most obvious implication of this is that you can write multiple
drivers to a net and expect the values to be properly resolved, and in
particular the HiZ value works as it should. So I am well on the way to
completing strength modeling support.
What is still missing is support for strength specifications in the
Verilog source. Although the parser supports the strength related keywords,
they are not passed on to elaboration, or used to generate drivers with
the proper strengths. So that's in the works.
While doing all this VVM rewrite, I've made the generated code considerably
smaller. And of course fewer templates are used. The upshot of this is that
compiles of larger designs should go a whole lot faster. This is important
because people are using Icarus Verilog for increasingly larger designs.
On some larger examples, I've achieved more then 3X compile time improvement.
Icarus Verilog 20000409 Snapshot:
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Named events now work! Event object declarations and trigger statements
are fully supported, and blocking on a single event also works. I'm not
up to named events in event lists because I'm in the midst of redesigning
the way events on nets and regs are implemented. However, the common case
works fine, so there you are.
I've also added support for some more arithmetic operators. Division and
Modulus now work in many contexts, and are not far from working everywhere.
Also, comparison operators work in places they used to not.
There was a compile error in memory objects that managed to slip through
a couple snapshots, that I finally cured. The problem was pretty gross,
but somehow not quite tickled by my tests. Oh well.
I've integrated some VCD improvements from Anthony Bybell. Some of you
recognize the name as the author of GTKWave, so if he says VCD works like
so, then that's how VCD works:-) Anyhow, he fixed the VCD output to be
more portable, and also a bit smaller when vectors are involved. He also
fixed some bugs with multiple calls to $dumpvars.
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Notable changes since the last pkg are (from the snapshot announcement):
Parameters are complete.
What this means is that I finally got around to supporting defparam,
and while I was at it I rewrote the entire parameter handling and added
the parameter support included in 1364-2000.
I have rewritten major portions of the VVM backend. The vvm_nexus class
has been introduced to the fray, and all the device implementations in
the VVM library now use the nexus to drive and receive values. An advantage
of this scheme is that the t-vvm backend code (in ivl proper) is simpler,
and so is the generated C++ code.
I also removed most of the template classes. This proved to be a huge
compile-time benefit (though compiling twice as fast really only matters
for large programs) and it doesn't seem likely to hurt run-time performance.
A few remain, either because they seemed harmless (the N-wide logic gates)
or I couldn't yet figure out a good way to replace them (vvm_bitset_t).
A side benefit of this is that the vvm library may now be a modeling
library that ordinary humans can use to write their models in C++. This
may provide the unexpected benefit of heading me towards incremental
compilation of designs. So who was it who was beating me over the head
asking for that?-)
I also fixed a few minor problems with the preprocessor. Those of you
who reported problems with `includes and `defines should check this out.
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of the cad/verilog package. Development snapshots are created quite frequently
in between stable releases.
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