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2016-10-08cad/verilog has been renamed to cad/iverilogkamil1-35/+0
Use saner and more specific name for this package. No objection for rename from <gdt>
2016-10-08Update cad/verilog (icarus verilog) from 0.9.7 to 10.1.1kamil1-53/+11
pkgsrc changes: - note GitHub tags (but not use them for now) - remove conflict with nonexistent verilog-current - install additional documentation in share/doc/ivl (not share/ivl) - drop DESTDIR gymnastics - build works without it - (re)enable gperf dependency - regenerate buildlink3.mk - drop patches/patch-lexor_keyword.cc - no longer needed - patches/patch-vpi_Makefile partially fixed upstream - rest not needed upstream changelog ================== Probably the only notes available: Here are the release notes for Icarus Verilog release branch 10. The 10 release is a huge improvement over the 0.9 release series, in every aspect. Much more of the Verilog and SystemVerilog language is supported, many bugs have been fixed, and performance has improved. The changes (improvements!) are so numerous that there is no point attempting to enumerate them. -- http://iverilog.wikia.com/wiki/Release_Notes_Icarus_Verilog_10
2016-07-24Fixed pkglint warnings about unknown sed commands.rillig1-7/+7
2016-06-01Force creation of dep directories to prevent race conditions during thejoerg1-1/+4
actual build.
2014-10-09Remove pkgviews: don't set PKG_INSTALLATION_TYPES in Makefiles.wiz1-3/+1
2014-06-28Work around build problem seen only in pbulk (remains unclear why).dholland1-2/+7
Disable build dependence on gperf as the build doesn't actually run it, and also for this workaround I need to patch the gperf output file.
2014-02-15Update HOMEPAGE.mef1-2/+2
2014-01-07(Upstream)mef1-4/+47
Icarus Verilog 0.9.7 is Available (August 26th, 2013) ----------------------------- The developers are pleased to announce the next stable release in the 0.9 series, version 0.9.7. Icarus Verilog is a mostly complete implementation of the hardware description language Verilog, as described in IEEE Std 1364-2005. It also includes a number of user requested extensions. It is freely available (open source), is supported on most operating systems, and will be available as a precompiled package for many of these systems. Icarus Verilog 0.9.7 is primarily a bug fix release. Therefore, we recommend people using the 0.9.6 or earlier releases upgrade to 0.9.7 as soon as possible. Version 0.9.7 is the recommended version for all new users. More details, including known limitations, deviation from IEEE Std 1364-2005, where to obtain the source code, and links to some of the precompiled packages can be found in the Release Notes located here: <http://iverilog.wikia.com/wiki/Release_Notes_Icarus_Verilog_0_9_7> (pkgsrc) 0.9.4 to 0.9.7 update and two patches are added for DESTDIR and 'mkdir: dep: Not a directory' problem.
2013-07-15* .include "../../devel/readline/buildlink3.mk" with USE_GNU_READLINE=yesryoon1-2/+3
are replaced with .include "../../devel/readline/buildlink3.mk", and USE_GNU_READLINE are removed, * .include "../../devel/readline/buildlink3.mk" without USE_GNU_READLINE are replaced with .include "../../mk/readline.buildlink3.mk".
2012-10-08Drop PKG_DESTDIR_SUPPORT setting, "user-destdir" is default these days.asau1-2/+1
2011-04-13update to 0.9.4drochner1-6/+3
changes: -Language Coverage: -Add support for using the &&, || and ! operators with real constant values -Add support for passing -0.0 from the compiler to the run time -Add support for parsing pull devices that have two strengths specified -Allow multiple attribute instances -bugfixes pkgsrc change: clean up DESTDIR support
2010-02-01DESTDIR supportjoerg1-1/+4
2009-05-20Recursive ABI depends update and PKGREVISION bump for readline-6.0 shlibwiz1-1/+2
major change. Reported by Robert Elz in PR 41345.
2009-03-11update to verilog-0.8.7, the latest in the stable 0.8 series.dmcmahill1-2/+2
Release Notes for Icarus Verilog 0.8.7 none (but see below for other releases since the last version in pkgsrc) Release Notes for Icarus Verilog 0.8.6 This is a bug fix update of the 0.8 stable version of Icarus Verilog. The v0.8 series tries to remain as stable as possible while still fixing bugs that are safe to fix. Preprocessor: * Fix parse/preprocess of C-style comments in surpressed ifdef blocks. * Support leading underscore in preprocessor names. Compilation/elaboration issues: * Support min:typ:max expressions in more places. * Fix handling of @* non-input nets. * Do not support system functions in continuous assignments. * Do not support converting vectors to real. * Do not support constant real valued expressions. Run-time ussues: * Fix comparison of negative numbers that happen to be equal. * Fix bad execution of certain expressions caused by code generator bad lookaside handling. * Proper error message for invalid bit selects. * Implement $printtimescale system task. Compiler build issues: * Compile OK evel if libbzip2 is not installed, but do not support LXT2 in that case. Release Notes for Icarus Verilog 0.8.5 This is mostly a bug-fix release for the 0.8 stable branch. * Fix assertions from unary operators with certain operand widths. * Fix incorrect comparison results when in certain cases comparing two signed negative integers. * Latch synthesis has been added to the core synthesizer * Add nand gate support to the edif code generator * Minor compile time errors/warnings * Improved messages from the configure script Release Notes for Icarus Verilog 0.8.4 This is a bug-fix release for the 0.8 stable branch. The 0.8 stable branch updates do not include significant new features (they go into the devel branch instead) nor fixes that are deemed to drastic to include in a stable tool. - Various source code portability problems have been fixed. The 0.8 no longer compiles on many modern systems. - Various bug reports have been put to rest with this release. Some parser errors have been fixed (including a few regressions from 0.8.3) and a few new syntaxes added. - A variety of systhesis bug fixes and enhancements are included in 0.8.4. Currently, synthesis is only actively supported in the 0.8 branch, and the 0.8.4 is the most complete.
2006-10-04update to verilog-0.8.3dmcmahill1-2/+2
** Release Notes for Icarus Verilog 0.8.3 This is a new release of the stable 0.8 branch. The changes from 0.8.2 are intended to be evolutionary, rather then revolutionary, to enhance the stability of the branch. Various simulator bugs have been fixed, including (but not limited to): - Detect overrun of timescale vs. precision - Handle more operators in constant expressions - Various ivl crashes and panics fixed. - Some performance bottlenecks have been fixed. - Various tool compilation problems have been fixed. Also, the internal synthesizer (for synthesis targets) has been considerably improved. NOTE that the code generators have not been improved to take advantage of all the changes here, so there is work yet to be done. The mingw build process for compiling in Windows has been reworked. It is now possible (indeed preferable) to compile fully native Icarus Verilog binaries on Windows with no Cygwin tools at all.
2006-05-28For building verilog, lex is indeed needed.rillig1-2/+2
2006-05-22Needs bison.joerg1-2/+2
2006-05-21Fixed pkglint warnings. Since bison and lex are not used when building,rillig1-4/+2
they don't need to be defined in USE_TOOLS.
2006-05-06update to verilog-0.8.2. Adds edif output, contains several bug fixes fordmcmahill1-3/+2
compatibility with more c++ compilers.
2006-02-05Recursive revision bump / recommended bump for gettext ABI change.joerg1-1/+2
2006-01-29add missing USE_LANGUAGESdmcmahill1-1/+3
2005-05-22Replace explicit build dependencies on bison and manipulations on thejlam1-7/+5
YACC variable with USE_TOOLS+=bison.
2005-05-22Remove USE_GNU_TOOLS and replace with the correct USE_TOOLS definitions:jlam1-2/+2
USE_GNU_TOOLS -> USE_TOOLS awk -> gawk m4 -> gm4 make -> gmake sed -> gsed yacc -> bison
2005-04-11Remove USE_BUILDLINK3 and NO_BUILDLINK; these are no longer used.tv1-2/+1
2005-03-02update to verilog-0.8.1. This is a minor bug fix releasedmcmahill1-2/+2
2004-10-14update to verilog-0.8.dmcmahill1-4/+7
The current release is a considerable improvement over the previous stable release. It includes 20 months of fixes and language coverage improvements. For a complete history of changes, see the release notes for individual snapshots between the 0.7 and 0.8 releases found at ftp://ftp.icarus.com/pub/eda/verilog/snapshots/pre-0.8 A brief list of highlights: - Support for advanced standard data types such as real, - Lots more language support in general, - Kernel of an extensible, interactive debugger is new, - More complete support for user supplied system functions and tasks, including PLI system functions with various return value types, - Better standards compliance for core system tasks and functions in general, including some Verilog 2001 file I/O support, and - Performance improvements in general.
2004-03-22add lex to the GNU_TOOLS list. Needed for SunOS and probably some others.dmcmahill1-2/+2
2004-03-12bl3ifydmcmahill1-7/+4
2004-01-22replace deprecated USE_GMAKE with USE_GNU_TOOLS+=make.grant1-2/+2
2004-01-02Require any version of gperf greater than 2.7.2.jmmv1-2/+2
2003-07-17s/netbsd.org/NetBSD.org/grant1-2/+2
2002-12-15update to verilog-0.7dmcmahill1-8/+5
This release represents many bug fixes, expanded language coverage, greatly enhanced xilinx fpga synthesis and several performance enhancements. The complete list is rather long.
2002-02-08update to verilog-0.6dmcmahill1-7/+14
WHAT'S NEW SINCE 0.5? Quite a lot. Innumerable bugs have been fixed, and standards coverage has been improved significantly. Warning and error messages have been improved, and so has compile performance. Gate delays, strength modeling, and floating point delays have all improved since the 0.5 release. If you had trouble with the 0.5 release, the 0.6 release probably fixes your problem. Support for large designs spanning multiple files has been improved dramatically. The usual preprocessor inclusion method still works, but The 0.6 release adds command files for keeping source file lists, and automatic library searches for missing modules. The library mechinisms are compatible with commercial tools, and commercial module libraries can be used with Icarus Verilog. Many compiler limitations related to the size and complexity of large designs have been relaxed or eliminated. There are no known design size limitations remaining in the compiler. Icarus Verilog should be able to handle any design that you have the patience to compile.
2001-09-27Mechanical changes to 375 files to change dependency patterns of the formjlam1-2/+2
foo-* to foo-[0-9]*. This is to cause the dependencies to match only the packages whose base package name is "foo", and not those named "foo-bar". A concrete example is p5-Net-* matching p5-Net-DNS as well as p5-Net. Also change dependency examples in Packages.txt to reflect this.
2001-08-04update to verilog-0.5dmcmahill1-5/+8
* The Big Change: VVP Past versions of Icarus Verilog performed simulation by compiling the Verilog design to intermediate C++ code, then in turn compiling that C++ (usually with G++) to a binary executable. This program was then executed to actually run the simulation. The 0.5 compiler, however, uses a custom internal language called "vvp." The vvp code generator writes a program in the vvp language that the vvp interpreter executes. This gets runtime performance similar to the older vvm method, but compile times are much faster. The result of this change is that there is a new program, ``vvp'', that is installed with the existing ``iverilog'' compiler. This program actually executes the simulation generated by the vvp code generator. There are manual pages for the iverilog command and the new vvp command, as well as a QUICK_START document to help you run your first simulation. * What Else Is New The compiler itself is now a lot more robust. While it still does not compile and understand the entire IEEE1364 standard, the compiler is less likely to crash on bad input, gives better error messages, and has generally been cleaned up.
2001-06-11CPPFLAGS is now passed to MAKE_ENV and CONFIGURE_ENV by bsd.pkg.mk, sojlam1-2/+1
adapt by moving CPPFLAGS settings to top-level, and removing explicit inclusion of CPPFLAGS into MAKE_ENV and CONFIGURE_ENV.
2001-04-11Use wildcards in CONFLICTS.wennmach1-2/+2
2001-03-27Change BUILD_DEPENDS semantics:hubertf1-3/+3
first component is now a package name+version/pattern, no more executable/patchname/whatnot. While there, introduce BUILD_USES_MSGFMT as shorthand to pull in devel/gettext unless /usr/bin/msgfmt exists (i.e. on post-1.5 -current). Patch by Alistair Crooks <agc@netbsd.org>
2001-02-16Update to new COMMENT style: COMMENT var in Makefile instead of pkg/COMMENT.wiz1-1/+2
2001-02-04update to verilog-0.4.dmcmahill1-9/+13
from the authors announcement: So many things have changed since version 0.3 that there is no point in listing them. There have been tons and tons of bug fixes and the language coverage is better, and so on and so forth. It's just so very much better then version 0.3:-) speaking as a user, some of my personal favorites are: - support for signed variables - iverilog now gives correct return codes (which makes 'make' much happier) for a more complete list, the commit messages for pkgsrc/cad/verilog-current/Makefile contain the changes for each development snapshot between verilog-0.3 and verilog-0.4
2000-06-22update to verilog-0.3dmcmahill1-9/+10
Changes, from the authors release statement, are: This release is a significant improvement over previous releases of Icarus Verilog, including better language coverage, improved synthesis, and increased performance. This release adds to the 0.2 release support for Verilog-2000 style parameters and parameter overrides, defparam, and localparam, including proper handling of scoping rules. Also, strength modeling is added, with support for strengths attached to gates and continuous assignments. Combinational user defined primitives have been added to complement synchronous primitives that were already supported. Support for primitives should now be fairly complete. Force/release/assign/deassign syntax now works properly, allowing for more sophisticated test bench design and debugging. Bug fixes have been numerous and varied. This release of Icarus Verilog is considerably more robust then previous versions, thanks to diligent testing and bug reporting by users all over the world.
2000-03-07Update to the released version 0.2 of verilog. I will be creating a seperatedmcmahill1-5/+8
verilog-current pkg to track development snapshots. This version has minor bug fixes over the previous snapshot package. Notable $display of a memory element now works correctly and a bug in $readmemb has been fixed.
2000-02-14update package to verilog-20000212. This release incorporates most of thedmcmahill1-2/+2
NetBSD pkgsrc patches to the previous release. Thanks to Stephen Williams (the author) for his willingness to accept patches!
2000-01-26Initial import of Icarus Verilog.dmcmahill1-0/+15
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well, and some -1999 features will creep in.
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