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The current release is a considerable improvement over the previous stable
release. It includes 20 months of fixes and language coverage improvements.
For a complete history of changes, see the release notes for individual
snapshots between the 0.7 and 0.8 releases found at
ftp://ftp.icarus.com/pub/eda/verilog/snapshots/pre-0.8
A brief list of highlights:
- Support for advanced standard data types such as real,
- Lots more language support in general,
- Kernel of an extensible, interactive debugger is new,
- More complete support for user supplied system functions and tasks,
including PLI system functions with various return value types,
- Better standards compliance for core system tasks and functions in
general, including some Verilog 2001 file I/O support, and
- Performance improvements in general.
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This release represents many bug fixes, expanded language coverage,
greatly enhanced xilinx fpga synthesis and several performance enhancements.
The complete list is rather long.
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WHAT'S NEW SINCE 0.5?
Quite a lot. Innumerable bugs have been fixed, and standards coverage
has been improved significantly. Warning and error messages have been
improved, and so has compile performance. Gate delays, strength
modeling, and floating point delays have all improved since the 0.5
release. If you had trouble with the 0.5 release, the 0.6 release
probably fixes your problem.
Support for large designs spanning multiple files has been improved
dramatically. The usual preprocessor inclusion method still works, but
The 0.6 release adds command files for keeping source file lists, and
automatic library searches for missing modules. The library mechinisms
are compatible with commercial tools, and commercial module libraries
can be used with Icarus Verilog.
Many compiler limitations related to the size and complexity of large
designs have been relaxed or eliminated. There are no known design
size limitations remaining in the compiler. Icarus Verilog should be
able to handle any design that you have the patience to compile.
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