pkgsrc - [no description]

Age	Commit message (Collapse)	Author	Files	Lines
2001-04-19	Move to sha1 digests, and add distfile sizes.	agc	1	-2/+3

2001-04-17	+ move the distfile digest/checksum value from files/md5 to distinfo	agc	3	-10/+8
	+ move the patch digest/checksum values from files/patch-sum to distinfo
2001-04-11	Use wildcards in CONFLICTS.	wennmach	1	-2/+2

2001-03-27	Change BUILD_DEPENDS semantics:	hubertf	1	-3/+3
	first component is now a package name+version/pattern, no more executable/patchname/whatnot. While there, introduce BUILD_USES_MSGFMT as shorthand to pull in devel/gettext unless /usr/bin/msgfmt exists (i.e. on post-1.5 -current). Patch by Alistair Crooks <agc@netbsd.org>
2001-02-16	Update to new COMMENT style: COMMENT var in Makefile instead of pkg/COMMENT.	wiz	2	-2/+2

2001-02-07	make sure the -I search path has the correct order to avoid picking	dmcmahill	5	-1/+92
	up a possibly out of date installed header from ${LOCALBASE}/include. Note that while we don't support installing a pkg when a previous version is installed, we should still be able to build it. Problem noted in private email from Lennart Augustsson.
2001-02-04	update to verilog-0.4.	dmcmahill	8	-105/+31
	from the authors announcement: So many things have changed since version 0.3 that there is no point in listing them. There have been tons and tons of bug fixes and the language coverage is better, and so on and so forth. It's just so very much better then version 0.3:-) speaking as a user, some of my personal favorites are: - support for signed variables - iverilog now gives correct return codes (which makes 'make' much happier) for a more complete list, the commit messages for pkgsrc/cad/verilog-current/Makefile contain the changes for each development snapshot between verilog-0.3 and verilog-0.4
2000-07-11	make iverilog give proper return codes.	dmcmahill	2	-1/+58

2000-06-30	make the default timescale in the output VCD files be 1ns for compatibility	dmcmahill	2	-1/+16
	with viewers such as Dinotrace.
2000-06-22	update to verilog-0.3	dmcmahill	7	-38/+38
	Changes, from the authors release statement, are: This release is a significant improvement over previous releases of Icarus Verilog, including better language coverage, improved synthesis, and increased performance. This release adds to the 0.2 release support for Verilog-2000 style parameters and parameter overrides, defparam, and localparam, including proper handling of scoping rules. Also, strength modeling is added, with support for strengths attached to gates and continuous assignments. Combinational user defined primitives have been added to complement synchronous primitives that were already supported. Support for primitives should now be fairly complete. Force/release/assign/deassign syntax now works properly, allowing for more sophisticated test bench design and debugging. Bug fixes have been numerous and varied. This release of Icarus Verilog is considerably more robust then previous versions, thanks to diligent testing and bug reporting by users all over the world.
2000-05-10	distinguish these 2 packages as "development snapshot" and "released" so	dmcmahill	1	-1/+1
	its more obvious of the difference.
2000-03-07	fix a bug in one of the patches that caused parse.cc to be built twice.	dmcmahill	2	-6/+7

2000-03-07	Update to the released version 0.2 of verilog. I will be creating a seperate	dmcmahill	2	-7/+10
	verilog-current pkg to track development snapshots. This version has minor bug fixes over the previous snapshot package. Notable $display of a memory element now works correctly and a bug in $readmemb has been fixed.
2000-02-14	update package to verilog-20000212. This release incorporates most of the	dmcmahill	14	-665/+21
	NetBSD pkgsrc patches to the previous release. Thanks to Stephen Williams (the author) for his willingness to accept patches!
2000-01-26	Initial import of Icarus Verilog.	dmcmahill	17	-0/+721
	Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well, and some -1999 features will creep in.