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2003-02-09s/${ENV}/${SETENV}/, noted by Kevin P. Neal in connection with PR 19586.wiz2-4/+4
2003-02-07unlimit datasize for builddmcmahill1-1/+2
2003-02-06enable optimization (use release settings)dmcmahill1-1/+7
2003-02-06repair botched patch filedmcmahill2-5/+5
2003-02-06update to ViPEC-3.1.3.dmcmahill7-194/+109
The previous version was extremely out of date and the distfile is no longer available. Many, many changes since the last packaged version. New 'tuner' feature added. New models added. Several bug fixes too numerous to list.
2003-02-05fix a bug when reading certain NC/Drill files. Files with leading +/-dmcmahill3-2/+21
are not properly parsed. Bump pkgrev.
2003-02-04update to covered-current-20021214 as part of fixing compile problems noteddmcmahill5-5/+58
in recent bulk builds. Release covered-20021214 made. This release is a bug fix release. See list below for details. Bugs that lead to infinite looping in the score command and segmentation faults should now be cleared up. Please let me know if there are any other bugs that need to be addressed before first stable release. Development documentation updated to match changes in files. Regression suite has been updated quite a bit from last time. There are now over 125 diagnostics in the regression suite (my goal was to write about 100 before first stable release). - Segmentation fault fixes in report command - Parser can now handle all net types (not just wire). Diagnostics added to regression suite to verify their proper handling. - Parser updated to handle net declaration assignments (e.g., wire a = b & c;). Diagnostics added to verify proper handling. - Added human-understandable error messages in parser to help identify file and line number along with a quasi-helpful error message description. - When parser error is found, Covered exits after parsing phase without continuing to write CDD file. - Fixed bug where a multi-bit select expression existed in a module that was instantiated more than once. Assertion error fired in this case. - Updated regression suite for VCS testing. - Fixed bug where parameters were used in modules that were instantiated more than once. - Fixed bug that dealt with parameters (see param6.1.v for test case). - Fixed bug where a delay statement was the last statement in a statement block used by Covered. Added diagnostics to verify correct behavior. - Fixed infinite loop problem with db_add_statement function. - Fixed infinite loop problem with statement_set_stop function. - Fixed bug with parsing order. When an instance is found for a module that has already been parsed, the instance was incorrectly being handled. Bug replicated with instance6.v diagnostic. - Fixed output of edge-triggered events to add @(...) around the expression (they were easily confused with other code that could exist on the same line). - Fixed bug in parser to not allow module to be parsed more than once. - Fixed bug that lead to an assertion error (see instance6.1.v for test case). - Fixing bug with calculating list and concatenation lengths when MBIT_SEL expressions were included. - Changed Covered's handling of -y directories. Before, all files in these directories were fed into the parser to look for missing modules. Now, when a module is needed, the module name is used to find the matching filename in the -y list (basically, the -y option works like the -y option in Icarus Verilog and VCS). This fix really streamlined the parsing phase and fixed several bugs. - Memory declarations are now properly ignored (produced segmentation fault previously). - Fixed report command to display all lines and expressions in order according to their line number (the problem is REALLY fixed now). - Removed hierarchical references from being scored. All in all, you should notice a huge improvement in the parsing speed, syntax errors are reported better, more Verilog syntax should be handled properly, the score command will run a bit faster than before, and the reports should be a bit easier to read. Segmentation faults and assertion errors should become lesser in number (if not gone altogether?). I am feeling pretty confident that we are getting close to a stable release as I have been able to generate a CDD file for a chip that is millions of gates in size (CDD file was created in the range of 30 - 45 seconds!) Keep the bug reports coming. I have some things to work on for next release already.
2003-02-04update to verilog-current-20030202.dmcmahill3-25/+12
This is the first packaged (in pkgsrc) snapshot after the verilog-0.7 release. This snapshot adds preliminary support for real variables to the language to the features already found in verilog-0.7.
2003-02-01Update to atlc-4.2.10dmcmahill3-43/+133
Many improvements such as support for mixed dielectric systems and several bitmap generators for common structures to allow quick application of the tool. Several bug fixes as well. Voltages outside a shield are set to zero which fixes a reported result in older versions. Many other improvemnts and bug fixes are listed in the ChangeLog in the distfile.
2003-01-28Instead of including bsd.pkg.install.mk directly in a package Makefile,jlam1-2/+2
have it be automatically included by bsd.pkg.mk if USE_PKGINSTALL is set to "YES". This enforces the requirement that bsd.pkg.install.mk be included at the end of a package Makefile. Idea suggested by Julio M. Merino Vidal <jmmv at menta.net>.
2003-01-27Remove dependancy on gnome1-dirs as discussed with wiz. This will be ↵jmmv1-2/+1
handled by gnome-libs.
2003-01-27Depend on gnome1-dirs to handle shared directories. Bump PKGREVISION.jmmv2-3/+7
2003-01-25Use buildlink2.jlam1-7/+4
2003-01-24Add INTERACTIVE_STAGE=fetch, since this package has a _FETCH_MESSAGE.wiz1-1/+3
2003-01-24Correct the directory path for GNU m4 package.agc1-2/+2
2003-01-13Needs GNU m4. Fixes bulk build problem.wiz1-1/+3
2003-01-10emacs.mk already includes bsd.prefs.mk, no need to include it manually awiz1-3/+1
second time.
2003-01-10USE_PKGLOCALEDIRcjep1-1/+2
2003-01-07Rename older (<1.6) Guile as guile14.uebayasi3-6/+6
Packages using Guile now all depend on guile14. These packages are expected to be made depend on newer Guile (1.6.x) when updated in the future.
2003-01-04Whitespace nitcjep1-2/+2
2003-01-03Change my email address to the NetBSD one (hispabsd.org -> netbsd.org).jmmv1-2/+2
Approved by wiz.
2002-12-28Bump PKGREVISION on packages that depend on x11/xforms, since therejschauma1-2/+2
has been a soname change. Pointed out by fredb.
2002-12-28Revert previous; the problem had been fixed by Jan Schaumann.uebayasi1-3/+1
2002-12-28Add missing dependencies.uebayasi2-2/+6
2002-12-26Add BUILD_DEPENDency on geda-symbols, to fix problems encountered duringjschauma2-2/+6
Huberts latest bulk-build.
2002-12-24Bump PKGREVISION because of dependency on latest freetype2 or glib2wiz1-2/+2
package and library major bumps therein. Also match dependency in corresponding buildlink2.mk's for the same reason. Mmmm, binary packages.
2002-12-23Wildcard m4 dependency.wiz2-4/+4
2002-12-18USE_GNU_GETTEXT allows this to build.grant1-1/+2
From pino@dohd.org in PR pkg/19437.
2002-12-15update to verilog-0.7dmcmahill3-22/+14
This release represents many bug fixes, expanded language coverage, greatly enhanced xilinx fpga synthesis and several performance enhancements. The complete list is rather long.
2002-12-14add and enable gdsreaderdmcmahill1-1/+2
2002-12-14import gdsreader-0.3dmcmahill5-0/+79
GDSreader - simple Calma (GDSii) parser/printer tool. This software has as target the printing/plotting/displaying of Calma (GDSii) files without using true layout editors. I had once to visualize an unknown Calma file and customizing LEdit or Magic (the two layout editors I had access to) was so difficult that I decided to write this program. Current status: - gdsreader is in an alpha stage and you should not expect too much from it; - the Calma files are almost completely parsed (had no layout example that makes use of BOX/NODE elements); - given a Calma structure name, a PostScript file and a HPGL/2 file are generated. The way each layer is handled is controlled by an ASCII configuration file. The properties that can be set are color, fill (only solid is supported), hatch (simple or cross, the angle and spacing are user customizable too). In order to produce an useful PostScript output, you need to write a configuration file (default is .layers.config). The one you'll find with the distribution is suitable for the Calma example test.gds (an actual Bandgap reference).
2002-12-13update the gEDA suite of tools to the 20021103 release.dmcmahill26-174/+417
This represents many many improvements and bug fixes. A few items to note are that the attributes used by the symbol library have been greately cleaned up and unified. You may want to run gsymupdate and gschemupdate if migrating from older versions of the tools.
2002-12-09Replace "true" by "${TRUE}".tron2-6/+6
2002-12-08add and enable covered-currentdmcmahill1-1/+2
2002-12-08initial import of covered-current-20021127.dmcmahill4-0/+50
This is a development snapshot. Packages of the released/stable versions will be imported as 'cad/covered' when available. Covered is a Verilog code coverage analysis tool that can be useful for determining how well a diagnostic test suite is covering the design under test. Typically in the design verification work flow, a design verification engineer will develop a self-checking test suite to verify design elements/functions specified by a design's specification document. When the test suite contains all of the tests required by the design specification, the test writer may be asking him/herself, "How much logic in the design is actually being exercised?", "Does my test suite cover all of the logic under test?", and "Am I done writing tests for the logic?". When the design verification gets to this point, it is often useful to get some metrics for determining logic coverage. This is where a code coverage utility, such as Covered, is very useful. Please note that this package is a development snapshot and while it contains the latest and greatest features, it may be buggy as well. There is a seperate package which is made of the stable releases.
2002-12-04Build-depend on libiconv; it is required to generate some files.jmmv1-1/+2
2002-11-30USE_PKGLOCALEDIR.salo2-7/+8
2002-11-22update to gerbv-0.11dmcmahill2-5/+8
Changes since last version: * fixed bug which caused huge memory usage and crashing when zooming way in to a layout * Two bugs in aperture macros fixed; one caused "multi macro" macros not to work properly and the other was related to primitive 20. * The Debian build system discovered that I checked if unsigned were -1. * Some cleanup/speedup when parsing Gerber by removing nested strncmp's with a switch/case. * RS274D caused segfault. * If %SR%, %SF% and %AS% are defined to their default values the compiler doesn't complain anymore. I still don't handle them if they are non default values. * In some strange corner case we managed to sometimes get spurious lines showing up on the image. * Strange drill files from Orcad386 handled better (we all know what Pitch thinks about Orcad:-) ). * Dino Ghilardi has contributed some code to be able to set the scale explicitly. That can be used when printing PNG's generated by gerbv. He has also written a text on how to actually get them out on the printer. It is in doc/PNG-print/PNGPrintMiniHowto.txt. * Round off when converting from inches to pixels changed so poured areas built up by several lines now seems to fill. Before the change you could, at certain zoom levels, see gaps that wasn't there.
2002-11-11Trivially use buildlink2.seb1-3/+3
2002-11-10add buildlink2.mk file in preparation for some coming pkgs which need itdmcmahill1-0/+36
2002-10-29add and enable tkgatedmcmahill1-1/+2
2002-10-29initial import of tkgate-1.6i provided in PR 18847 by Julio Merino,dmcmahill6-0/+452
jmmv at menta dot net. TkGate is a digital circuit editor and simulator with a Tcl/Tk based interface. TkGate includes a large number of built-in devices including basic gates, memories, ttys and modules for hierarchical design. The simulator can be controlled either interactively or through a simulation script. Memory contents can be loaded from files, and a microcode/macrocode compiler (gmac) is included to create tkgate memory files from a high-level description. The simulator supports continous simulation, single step simulation (by clock or epoch) and breakpoints. Save files are in a Verilog-like format. TkGate also includes a number of tutorial and example circuits which can be loaded through the "Help" menu. The examples range from a simple gate-level 3-bit adder to a 16-bit CPU programmed to play the "Animals" game. TkGate has a multi-langauge interface with support for English, Japanese, French and Spanish.
2002-10-22update to verilog-current-20021019dmcmahill3-31/+5
Release Notes for Icarus Verilog Snapshot 20021019 The synthesizer now detects asynchronous set/reset inputs to DFF devices. The fpga and vvp code generators have been updated to support these signals. The vvp code generator also gained some register management code that improves the thread register usage. This redoces code size for certain common cases, and thus improves simulation performance. The requirements on `ifdef and related compiler directives has been relaxed, to correspond to more common behavior. The parameter range support crashed if the range expressions had parameters in them. This is fixed, and some signed-ness bugs fixed along with it. Rearrange some of the configure script tests to assure better compatibility accross platforms.
2002-10-17fix the iverilog-vpi shell script (bash-isms)dmcmahill3-2/+28
2002-10-16update to gerbv-0.0.10dmcmahill2-6/+5
Yet another bunch of bugs in different corner cases of Gerber files has been fixed. Many fixes in polygon area fill, some fixes in calculating circles, a statically allocated array caused strange stray segfaults when drawing aperture macros. A bunch of new command line switches. Most important are: * --display: use as in all other X-programs, ie open window from a remote computer. * --geometry: Sets the geometry. Usually gerbv guess the resolution of your window and sets the window size accordingly. If you for instance have a bigger virtual window than actual screen the window can get quite big. With this switch you can override with for example --geometry=400x300 Fixes in drill file parser. Many drill files don't have drill sizes in them, else perfectly valid files. Pitch fix makes gerbv parse drill files even though they don't have drill sizes defined, but under protest. Greatest fix of them all. Super imposing. Handles paint-scratch-paint more proper. Changed dramatically how different layers are drawn "on top of each other".
2002-10-14Dan maintains gEDA these days.rh7-14/+14
2002-10-14add and enable verilog-modedmcmahill1-1/+2
2002-10-14initial import of verilog-mode-3.60dmcmahill5-0/+60
This is a major mode for editing Verilog HDL source code under GNU Emacs or XEmacs.
2002-10-14update to dinotrace-9.1hdmcmahill2-5/+5
Changes in Dinotrace 9.1h 08/30/2002 *** Save_duplicates is now on by default. **** Fixed several bugs when save_duplicates is enabled. **** Updated Windows install. [Greg Loxtercamp] **** Fixed coredump reading wide ascii traces. [Vitaly Oratovsky]
2002-10-13update to verilog-current-20020921 snapshot. Many improvemnts in thedmcmahill2-5/+5
synthesis code and bug fixes in the simulation code since the last packaged snapshot.