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* A new part: wire jumper.
* Drag'n'drop from the part preview to place parts.
* A crude form of auto numbering when placing parts.
* Cleaned up makefiles and put some samples in
*<prefix>/share/oregano/samples/.
* Changed default spice executable name to spice3.
* Connection dots.
* A simple voltmeter function.
* Fix various ref/unref/sink design flaws, to
increased stability.
* Part browser remembers the previously selected part
when switching libraries.
* Should really work with libxml 2.x this time... :-)
* Reorganization of installation directories for model
and library files.
* The plot widget now features axis values.
* New parts: uA741 opamp and a simple zener diode.
* Parts and wires can be flipped horizontally and vertically.
* Enabled loading of simulation settings again.
* Added a simple text label item to put text on the sheet.
* Fixed the 'sometimes non-disappearing floating item' bug.
* Should now also work with libxml 2.x (untested).
* Switched C and B on the BJT transistor models.
* Removed the unfinished printing support for now.
* Redesign of lots of internals.
* Added lots of functionality to the parts library,
such as model files, and conditional values in templates.
* Improved a few of the icons.
* Fixed a bug where the name of the markers could not be edited.
* You can inspect the connection span, by holding Control while
moving the cursor over wires.
* Added the ability to rotate parts while placing them; press 'r'
to achieve this.
* Logging of Spice warnings and errors during simulation.
The messages can be shown in a log window.
* Beautification of the part browser UI.
* Added more tooltips and updated some translations.
* Fixed a few non-critical bugs.
* New and improved part properties editor.
* Improved user interface for the plot window.
* Internationalization fixes to netlist generation
and schematic loading/saving.
* The simulation now uses the user supplied time step size.
* French translation from David Monniaux.
* Even more refinement of the default library symbols/parts.
* Mission 'Code Cleaning' continues.
* Cut/copy/paste is implemented.
* The symbols are redrawn to look much nicer and more standard.
* Some new symbols, e.g. MOSFETs.
* There can be more than one part library, thanks to Elker Cavina.
* A bug with simulation time settings was fixed.
* There is a problem with some spice packages, that make them generate
binary output, even though the default should be ascii. This is now
fixed by telling spice to always output text.
* The help files are now installed in the rpm package.
* Lots of code restructuring and cleaning.
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don't know what happened the first try.
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changes since the last packaged version (from the authors announcements):
Icarus Verilog snapshot 20001119
--------------------------------
The big change here (code wise) is improved and corrected constant
propagation. I was missing OR, NOR, NAND and XOR propagations, and
got some of the AND calculations wrong. This fixes this shortcoming
and in some cases this actually may speed up your compile a tiny bit.
Some more dangling signals are also eliminated.
supply nets are now working (PR#17). They also will trigger constant
propagation (as they have constant values) in certain cases.
Those of you doing cygwin compiles have trouble compiling parse.cc. I've
put into the cygwin.txt some slightly better instructions for dealing with
this situation, when it comes up.
I've also added missing symbols to ivl.def, so that tgt-stub properly
links.
Icarus Verilog snapshot 20001112
--------------------------------
This snapshot includes support for MOS et al devices as contributed
by Tim Leight. It appears to actually work as advertised, and I also
have from him a collection of tests that I'll be adding to the test
suite as soon as I get copyright information from him. So if you have
been dreaming of simulating MOS devices with Icarus Verilog, give this
a try. This update also fixed PR#27.
I've also cleared up a few bugs related to unconnected module ports.
Module port syntax is pretty byzantine, as PR#38 shows.
The loadable target API has gained access to flip-flops. This is required
for PLD code generation to work. I think the ivl_target API now supports
the minimum devices needed to generate PLD files, and I'm on to the task
of getting ancillary PAL support working.
Icarus Verilog snapshot 20001104
--------------------------------
Yes, I've managed to find the right bits to get Icarus Verilog to compile
on RedHat 7.0, and this snapshot includes those fixes. It took some back-
and-forth with tech support at RedHat to get it going.
I've also fixed up make check so that it works in general. If you use
"make check" after building, the makefile will run the examples/hello.vl
program through the local parts to make sure they minimally work.
I've added support for the "time" data time and more complete support
for the $time system function. These should work properly in all cases
now, so cases of not working are worthy of a bug report.
I've also integrated a re-implementation of sequential UDPs from Stephan
Boettcher, so I would appreciate it if all you folks using primitives
give this a fresh test. (It should be an improvement.)
This is a relatively small message, which doesn't reflect the complexity
of the changes. The "time" support in particular caused a lot of threads
to be pulled. Also, I've been doing some PLD stuff on the side, so I've
been busy.
I've also knocked of PR#11, 14, 33, 34, 39 and a few other bugs.
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changes (from the announcement):
The libipal library has gained access to more structural information
about the device, including enable SOPs. It is also now possible to
lookup a SOP by name and by pin. Also, access to sop fuse positions
has been improved.
The toplevel makefiles were changed to use $(MAKE) instead of make.
There are a few other niggling makefile fixes as well.
ipalrev and ipaledit now both take the -p flag allowing you to choose
the architecture for your device, and there are now two devices to
choose from. (both 22v10s:-)
ipalrev was seriously confused about inversions and the sense of things,
but that should be all cleared up now. It does a decent, if not complete,
job of decompiling 22v10 designs.
And finally, the PA file format has been extended to accommodate the
new library features, and PA files are now named according to a naming
convention for identifying devices.
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from the NEWS file:
New in 20001123:
- Saving wave and panel configuration as guile scripts.
- Executing guile scripts from menu or command line (-s <script> option)
- Remote control using the gwave-exec and gwaverepl utilities
New in 20001004:
- Spice3/Ngspice rawfile improvements: binary files now work!
- Other minor file-reading improvements.
- spice source code to examples for which I could still find it.
New in 20001004:
- Major improvements to handling of binary files produced by HSPICE.
- Overhaul of input of spice3/ngspice raw files; more robust and tolerant
of complex numbers.
- User interface improvements: tooltips added. User's .gwaverc no longer
required to do lots of standard setup. system.gwaverc can be copied
to $HOME/.gwaverc and edited to taste.
- sp2sp utility included for converting any spice file readable by gwave into
a convenient tabular ascii format.
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from the NEWS file:
* Changes in Dinotrace 9.0l 8/30/2000
** Added support for femtosecond Verilog timescales [Derek Bosch]
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from the history file:
----------------------
New features:
1. New probes: diode G, mos IBD, IBS, GBD, GBS.
2. New options: "floor" and "vfloor". (Floor was in the manual, but
not in the simulator.)
Improvements, bug fixes, etc.
1. There is a change to the way behavioral modeling conditionals are
handled. It should now be 100% compatible with SPICE, considering the
subset that duplicates SPICE. There are still significant extensions
beyond SPICE, particularly that you can have behavioral resistors,
capacitors, inductors, etc.
2. Parameter default calculations are now done in a manner consistent
with Spice 3f5. Previously, it was supposedly consistent with Spice
2g6.
3. A bug in calculation of threshold voltage of the level 6 model, for
P channel devices, has been fixed.
4. A bug in calculation of Meyer capacitances when the device is
reversed has been fixed. This bug sometimes caused a discontinuity at
vds=0.
5. I have added some smoothing to the Meyer mos capacitor models.
This improves convergence. The down side is that sometimes the
answers are different. It is probably a little better, when
considering closeness to reality, but it is still Meyer's model.
6. MOSFET parasitic diodes are now the same as those used in Spice.
7. There are subtle changes in the diode model. I think this usually
improves convergence.
8. Charge calculation in Meyer capacitors and diode capacitiors is now
supposedly Spice 3 compatible.
9. An error in BSIM3 scaling has been fixed.
Some things that are still partially implemented:
1. Internal element: non-quasi-static poly-capacitor.
2. BSIM models, charge effects.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. The makefile does not set up the proper link for the model
compiler. You need to do it manually.
3. A bad setting of "vmax" and "vmin" can lead to convergence to a
nonsense result. It is not as bad now as it used to be.
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note, this is the development snapshot version of the package. As stable
releases become available, there will be a ipal package.
from DESCR:
Icarus PAL is a set of libraries and utilities for manipulating PAL
designs. The design information is conveyed in the industry standard
JEDEC file format.
Icarus PAL accepts parts descriptions that detail the device
structure, capabilities and pinouts so that software can be written to
work relatively independent of the part type. These parts descriptions
also describe how the fuses of a device are arranged, so that
synthesis tools can generate fuse maps to get the desired
functionality and pinout. See as a commented example the description
in the pa/pal22v10.pa description.
The ipaledit program takes as input a .JED file and displays the PAL
design. It shows the sum-of-products as a fuse matrix, and shows the
macrocell configurations in convenient form.
The ipalrev program takes as input a .JED file and reverse compiles
it, producing a Verilog program that logically describes the
design. This use useful for moving old designs to new tools.
Please note that this package is a development snapshot and while it contains
the latest and greatest features, it may be buggy as well. When
available there will be a seperate ipal package which will be made of
the stable releases.
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from DESCR:
The program is a viewer and editor for:
-GDSII files, KEY files (own made extended GDSII in ascii format) and
DAVID MANN files (flash format for mask plotting)
Features:
-It allows to draw primitives on a chosen layer, and to manipulate them.
-stack oriented tools allows zooming while drawing new primitives and
editing them. This also makes it possible to draw extremely accurate.
-primitives on the layers or/can be transparent colors and fill patterns
can be set on a layer basis
-drawing order of layers can be changed
-a hiearchy of pictures, named structures, can be handled and manipulated
-saving as a bitmap and other formats.
-measuring distances
-adding user defined properties to primitives
-boolean OR AND EXOR A-B B-A
-positive and negative process offset
-circle recognition in polygon and polyline data.
-move copy delete etc.
-transformations (scaling , rotation , moving)
-flatten the hiearchy of the drawing
-drivers for CNC (laser and milling machinery)
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NG-SPICE is the program being developed as the replacement for Berkeley
SPICE. Using the Berkeley code as a starting point, the NG-SPICE team
is working on improving the build system, adding to the models, and
improving the analysis capability.
SPICE is a general-purpose circuit simulation program for nonlinear dc,
nonlinear transient, and linear ac analyses. Circuits may contain resistors,
capacitors, inductors, mutual inductors, independent voltage and current
sources, four types of dependent sources, lossless and lossy transmission
lines (two separate implementations), switches, uniform distributed RC
lines, and the five most common semiconductor devices: diodes, BJTs, JFETs,
MESFETs, and MOSFETs.
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The program xcircuit is a generic drawing program tailored especially
for making publication-quality renderings of circuit diagrams (hence
the name). The output is pure PostScript, and the graphical interface
attempts to maintain as much consistency as possible between the X11
window rendering and the final printer output.
xcircuit is mouse, menu, and keyboard-driven, with the emphasis on
single-character keyboard macros.
Package provided by Jason Beegan <jasontd@indigo.ie> in PR 11383 with
some minor modifications by me.
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Jason Beegan <jasontd@indigo.ie> in PR pkg/11407
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from the authors announcement:
-----------------------------
The loadable target module API is starting to take shape.
That is the major thrust nowadays with Icarus Verilog, after all, so
progress is being made here. The biggest change is in fact a philosophy
change. The target module now needs only a single symbol -- target_design --
to receive the whole design. The target module can from there and using
the API access the entire design randomly. So if you wanted to implement
a graphical browser, you could:-)
I've added support for the l-values of procedural assignments, and also
back pointers to objects that reference ivl_nexus_t objects. This closes
the loop so that there should be no dead-ends in the design.
I've clarified and expanded the descriptions in the ivl_target.h header
file. There should be just about enough documentation to properly used
all the various types. (Have any of you tried to write GIMP plug-ins?
Have you looked at the libgimp header files? Have you seen any comments
there?-( I won't ever sink to that level, I hope.)
I've also imtegrated updates to the Cygwin32 port to support loadable
targets under Cygwin32. After much struggling, Venkat managed to discover
the secret magic needed to get load time symbol binding to work. Hopefully
I didn't break it too bad when I changed the API again. (I think it is
still fine.)
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circuit board editor.
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pkgsrc for this pkg be nearly 1Mb. Thanks to Thomas Klausner for pointing
this out.
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the resulting manpage as a file.
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as files instead of requiring the user to install one of our largest packages
just to build them. Note, in the previous version of this pkg, the docs generated
with latex weren't even being installed (!).
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Notable changes since the last pkged version are:
Gwave NEWS --- history of user-visible changes. -*- text -*-
New in 20000518:
- Logarithmic scales working on both X and Y axis.
New in 20000509:
- First public guile/guile-gtk release.
- Popup menu on visible-wave button can activate per-waveform dialog box
- Logarithmic scale on Y axis working; on X axis it isn't quite there yet.
New in 20000108:
- Merged in guile and guile-gtk; the GUI is mostly written in guile now.
- Some additional improvements to reading of HSPICE input. Reading partial
files from simulations still in progress works for ascii .tr0 files.
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Qt program on ELF platforms.
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Changes included in version 2.0.4
---------------------------------
- Fixed printing under windows.
- You can now plot the real and imaginary parts of the
circuit input and output impedances
Changes included in version 2.0.3
---------------------------------
- Moved to Qt version 2.1.0
- The help browser is now integrated into the ViPEC application.
- Fixed a bug in calculating the circuit output impedance.
- Input and output impedances ouput to a graph now works.
Changes included in version 2.0.2
---------------------------------
- Improved data storage of graphs and Smith charts
- Double buffering implemented for drawing of graphs
and Smith charts to reduce flicker.
- Improved font management
- Fixed display bug in Table view
- Fixed bug with output to 2 port parameter files under Windows
- Added support for Group Delay, see help files for more details
as well as sample circuit: group_delay.ckt
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ACS 0.27 release notes (06/03/2000)
New features:
1. BSIM3 model, DC.
They work for AC and transient analysis, but only the DC effects
actually work. The next release should have the charge effects. For
now, it fakes it with Meyer's model.
2. A first cut at a model compiler, to aid in development of new
models. Models are described in a ".model" file, which is processed
to automatically generate the ".h" and ".cc" files. This version
fully handles the ".model" statement part of it, but leaves the device
and common sections the old way. Eventually, the entire process will
be automated. The old way still works.
3. "Fit" behavioral modeling function, which fits a curve to a set of
data. You can specify the order of the fit, which is piecewise
polynomials. For now, the order may be 1 (linear, like PWL) or 3
(cubic splines). You may also specify the boundary consitions.
4. More probes.
Some things that are partially implemented:
1. Internal element: non-quasi-static poly-capacitor. It is needed by
the BSIM3 and EKV models. Eventually, it will be available as a
netlist item, but not yet.
Bug fixes:
1. PWL could fail if there were duplicate points at the beginning. It
still does, but gives a reasonable error message.
2. Some "dot commands" were ignored if there were spaces before the
dot. This was particularly annoying if the line was supposed to be
".end" which should make it exit. It didn't, leaving it in
interactive mode, a major annoyance in a script.
Other improvements:
1. There is a change to the way integration in capacitors is done. It
is now strictly based on charge (i = dq/dt). The old version was
based on capacitance (i = C * dv/dt) which is strictly incorrect. The
dC/dt term was missing (i = C * dv/dt + v * dC/dt). This is a
non-issue when C is constant.
2. More documentation on internals.
Changes that I think are improvements, but some may disagree:
1. The command line is a little different. In the old version,
"acs file" would run it, and whether it exited or not depended on
whether there was an ".end" line. Now, by default, it just loads the
file in preparation for interactive use. If you want batch mode, say
"acs -b file".
2. The regression suite is included in the standard distribution.
Changes that are not really improvements:
1. Due to the model compiler, the build process is a little more
complicated. To do a complete build, you must build the model
compiler first, then the simulator. If you are not making any new
models, you can probably get away with just building the simulator.
This will change in a future release.
Bugs:
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. The makefile does not set up the proper link for the model
compiler. You need to do it manually.
Hot items for a future release (no promises, but highly probable):
1. Charge effects in BSIM models. They are computed, but not loaded
to the matrix.
2. Completion of model compiler, and its documentation.
3. Completion of multi-rate.
4. Homotopy methods to improve convergence.
5. Transmission line accuracy and speed improvements, using a step
control mechanism similar to that used for capacitors.
6. Parameterized subcircuits and defined parameters.
7. A "trigger" element, so time dependent values can be triggered by
the circuit, as an alternate to simple time.
To reach me, try this email address:
aldavis@ieee.org
ACS ftp sites:
ftp://ftp.geda.seul.org/pub/geda/dist/acs-0.27.tar.gz
http://www.geda.seul.org/dist/acs-0.27.tar.gz
ftp://sunsite.unc.edu/pub/Linux/apps/circuits/acs-0.27.tar.gz
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up some possible conflicting headers.
- while I'm here, make me the maintainer (instead of 'packages')
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Use LTCONFIG_OVERRIDE for fewer patches.
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If anywhere, it should be the value of MAINTAINER in the Makefile.
Some minor cleanup/reformatting while I'm here.
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Hopefully fixes pkg/9873 (awaiting confirmation from the author of the PR)
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XXX: We really need a supported way to list a specific package for
XXX: build dependencies.
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are (from the authors announcements):
--------------------------------
Icarus Verilog snapshot 20000721
--------------------------------
(first snapshot after the 0.3 release)
This snapshot adds no new features or language support, but is working
towards more precise interpretation of scheduling and value propagation
details.
The first thing I've done is redesign the internal Link structure that
is used to connect the internal netlist together. There are some aspects
of the nexos of a set of links that were carried by the Link class or
by external functions. These have been moved to the new Nexus class and
linking and structure has improved because of it.
This has led me to modify the handing of signal initial values. In practice,
the time-0 value of a net is a property of the nexus instead of the objects
that are connected together, so I have implemented it so, and in the
process fixed a bunch of initial value problems.
One new feature that is added is support for non-constant delay expressions.
Now, you can even have something like ``#($random%256) <statement>'' and
expect it to do what you think. (So now the telephone example in James
Lee's "Verilog Qickstart" actually works!)
I've added some missing support for various operators in constant expressions.
I've also added some more of the friends of $random for those folks who
do stochastic modeling.
Constant propagation carries some new bug fixes, and some new smarts. It
is for example able to detect a mux with a constant 'bz input and replace
it with bufif devices, and other clevernesses with logic reduction.
--------------------------------
Icarus Verilog snapshot 20000729
--------------------------------
Like I said, the `timescale compiler directive now more or less works.
You can now specify timescale for modules, and the compiler will figure
out a global design resolution and scale your time values to match. The
VCD dumps should reflect the chosen resolution automatically. Floating
point notation is not yet supported, we'll see if that turns out to be
a problem.
A problem with `timescale support is that the compiler will allow unitless
modules. This can happen if you have `timescale late in the source file.
The default unit is the not-very-intuitive 1s. Frankly, I don't like the
`timescale semantics for this sort of reason, but its an accepted
standard, so I'm stuck with it.
I've also added support for min:typ:max expressions. The compiler chooses
one of the three expressions at compile time, based on a compile time
switch. You can ask for min typ or max values via the "-Tmin" etc. switch
to the iverilog command. If you do not specify a switch, the compiler will
choose the typ values but print warnings. The -Ttyp switch will suppress
the warnings.
I have fixed yet more net initialization bugs. These are getting pretty
subtle, now, so you should have a hard time tickling any remaining errors
here. I've also fixed a nasty and subtle bug in event expression support.
This bug only happened when the design had many event expressions with
many conjunctions.
Although they are not ready for use, I have made some forward progress
with disable statements. I now at least elaborate them, so now I just need
to figure out how to make the run-time work out. That's the hard part,
I'm afraid.
--------------------------------
Icarus Verilog snapshot 20000805
--------------------------------
I've finally dealt with a problem that's been nagging at me for a while.
Until now, it has been possible that excessively clever hierarchical
references into and out of task scopes could confound symbol lookup.
I think I finally put that to rest, and in the process reorganized the
netlist format for holding task definitions. It should no longer be
possible to confuse name binding in Icarus Verilog.
Found and fixed a silly bug in elaborating e?a:'bz and e?'bz:a expressions
into bufifN devices. I got the sense of the enable wrong in one of the
cases. All fixed (and the test suite updated to catch this silly mistake:-)
tri0 and tri1 nets should now work properly. These are mostly a run-
time issue which I solved using resolution functions. This is actually
a technique that I borrowed from VHDL.
For those of you doing XNF synthesis, I fixed up my FF/RAM detector to
allow <= assignments in always blocks. This is in fact the preferred way
to describe DFFs as <= more accurately simulates their RTL nature.
Also found and fixed a few DOS \r\n line end issues in the lexical ana-
lyser and the preprocessor. We sometimes forget how tricky these line-
end problems can be, and compiler directives are the most susceptible.
This problem most likely occurs when you transport files from a DOS
environment. (The MAC folks haven't complained much, so either I got it
right for them, or Kato took care of the problems for me:-)
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random crap. Hopefully fixes PR 9873 by Michael Wolfson
<mw34@cornell.edu>.
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Changes since 9.0g are (from the NEWS file):
Changes in Dinotrace 9.0k 7/17/2000
Fixed bug with $comment after $enddefinitions. [Harunobu Miyashita]
Fixed Tempest reading signals over 128 bits. [Ta-Chung Chang]
This bug was introduced in 9.0i.
Fixed portability bug with Value Examine showing 0s. [Ta-Chung Chang]
Fixed Verilog reading with large time intervals. [Matthias Wenzel]
Changes in Dinotrace 9.0i 5/1/2000
Major speed improvement in reading Tempest traces.
All trace formats now have less processing when building busses from
individual bits. [Steve Hoover]
ASCII traces assume extra time so last line is not lost.
ASCII traces which had timestamps would not show the last state of the
bus, as Dinotrace did not guess at how long that last state was valid for.
Now, it looks at the smallest time step in the trace, and uses that
as a guess at the timescale. [Pani Kodandapani]
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which takes entries of the format <make-definition-name>=<pkgname>. This
has not been added to MAKEFLAGS because (a) premature optimisation is the
root of all evil, and (b) because the .for loop used to implement this
shows the wrong results when multiple prefices are evaluated.
Modify all the package Makefiles to use EVAL_PREFIX, thereby simplifying
them considerably.
ALso simplify the logic to calculate the prefix as well.
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package's prefix would not work as part of the environment specification
via MAKE_ENV (as it would not be executed in the correct directory).
Fix this by invoking pkg_info(1) directly, not via an intermediate make(1)
step - this is not as clean, but more effective (i.e. it works).
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a bit more user-friendly.
Introduce a show-{gtk+,imlib,kdebase,qt1,qt2,xpm}-prefix target in
bsd.pkg.mk, and use "${MAKE} show-*-prefix" in package Makefiles.
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