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rmdir -> ${RMDIR}
rm -> ${RM} (${RM} added to PLIST_SUBST)
chmod -> ${CHMOD}
chown -> ${CHOWN}
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Changes in Dinotrace 9.1g 01/24/2002
*** Reread all traces on receiving a USR1 signal. [Uwe Bonnes]
**** Allow value searches on one-bit signals. [Vitaly Oratovsky]
Changes in Dinotrace 9.1f 01/08/2002
*** Let right button terminate Zoom click. [Uwe Bonnes]
**** Fixed Emacs 21.0 incompatibility with back-annotation.
**** Hacked around bug causing window manager crash when
using Examine inside Zoom. [Uwe Bonnes]
* Changes in Dinotrace 9.1e 11/16/2001
*** Allow 1-bit wide signals to have statenames. [Dominik Strasser]
*** Eliminate common prefix from postscript dumps. [Dominik Strasser]
*** Show count of posedges and negedges in value examine.
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What's new in 0.0.7
- Aperture macros!
- Improved detection of drill- or gerber file.
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WHAT'S NEW SINCE 0.5?
Quite a lot. Innumerable bugs have been fixed, and standards coverage
has been improved significantly. Warning and error messages have been
improved, and so has compile performance. Gate delays, strength
modeling, and floating point delays have all improved since the 0.5
release. If you had trouble with the 0.5 release, the 0.6 release
probably fixes your problem.
Support for large designs spanning multiple files has been improved
dramatically. The usual preprocessor inclusion method still works, but
The 0.6 release adds command files for keeping source file lists, and
automatic library searches for missing modules. The library mechinisms
are compatible with commercial tools, and commercial module libraries
can be used with Icarus Verilog.
Many compiler limitations related to the size and complexity of large
designs have been relaxed or eliminated. There are no known design
size limitations remaining in the compiler. Icarus Verilog should be
able to handle any design that you have the patience to compile.
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Make the print-PLIST target output ${MKDIR} also.
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programs such as mkfontdir use ${X11BASE} instead.
Also pick up a couple of /bin/chmod -> ${CHMOD}s
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A pkgsrc specific change is that it no longer conflicts with the
cad/spice package allowing both to be installed.
From the NEWS file:
This is a major release in terms of bug-fixes. Some enhancements
have been included: BSIM4 model and support for EKV model. The
source code for the latter must be obtained from EKV web site
(see DEVICE for more info). To enable EKV support you have
to obtain the code first and then use the configure switch
"--enable-ekv".
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many many changes since the last packaged snapshot.
A brief sampling of the changes (which include many bug fixes and
enhancements) is:
A variety of little problems with $display format strings have been
fixed.
The % operand should now simulate properly. Also, the * operator is a
little bit more optimized, and works in constant expressions.
Several bugs in strength modeling have been fixed. This includes drive
strengths on continuous assignments, which in the past generated code
without the strengths. Also, vvp gained some missing support for
constants with strength. I think that strength modeling is now
complete.
vpi_get_vlog_info support has been added to the vvp run-time. This is
a PLI function that allows access to run-time command flags. Also, vpi
access to root modules now works properly.
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changes since 0.0.5:
- Turn on and off explicit layers.
- Color on button reflect color on layer.
- Automatic detection of drill- or gerber file.
- Tooltips over buttons to reflect loaded filename.
- Handles Polygon Area Fill
- Major rehacking of file IO and pan code to significantly
increase speed.
- Autoscaling. Loaded gerber files are automagically scaled and
panned to fit in window. Also possible to do with loaded files
with Zoom/Fit meny option.
- configure.in enhancement to support package building in Red Hat.
Thanks to Wojciech Kazubski for patch.
- bzero changed to memset, which hopefully is more POSIX (for portability).
- Loads of bugs squashed and hopefully fewer added.
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Many changes since the last packaged snapshot. A sampling of these are:
Support for hierarchical names has been largely rewritten. The major
consequence of this is that escaped names now have much better
support. By now, most any combination of escaped and hierarchical name
should work properly, for nets, parameters, and anything else.
Output delays for primitive gates, including user defined primitivies,
should now work properly. Delays on nets still do not work, although
the parser now parses them and prints a "sorry" message.
Bugs in support for division(/) and modulus (%) have been fixed.
Bugs in l-values of synthesized DFF devices have been fixed. These
bugs were related to part selects of vectors in l-values.
A few XNF code generator bugs and limitations were fixed.
And as usual, a variety of miscellaneous bugs have been fixed in this
snapshot.
The bit size of the results of some unary redunction operators is now
properly handled. Also, similar problems with logical functions have
been fixed.
force/release now works for variables, though not yet for
nets. Assign/deassign already work.
many other bugfixes
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needs a LICENSE set to no-redistribution to flag it
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pkgsrc. Instead, a new variable PKGREVISION is invented that can get
bumped independent of DISTNAME and PKGNAME.
Example #1:
DISTNAME= foo-X.Y
PKGREVISION= Z
=> PKGNAME= foo-X.YnbZ
Example #2:
DISTNAME= barthing-X.Y
PKGNAME= bar-X.Y
PKGREVISION= Z
=> PKGNAME= bar=X.YnbZ (!)
On subsequent changes, only PKGREVISION needs to be bumped, no more risk
of getting DISTNAME changed accidentally.
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Mcalc is a JavaScript based calculator for accurate microstrip
transmission line analysis and synthesis.
The electrical parameters may be determined from specified physical
parameters, or the physical parameters required to meet a given set of
electrical parameters may be found.
Much attention has been given to making mcalc the most accurate online
based calculator short of a full electromagnetic simulation.
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GnuCap is a general purpose circuit simulator. GnuCap was
formerly known as ACS. GnuCap performs nonlinear
dc and transient analyses, fourier analysis, and ac analysis
linearized at an operating point. It is fully interactive and
command driven. It can also be run in batch mode or as a server.
The output is produced as it simulates. Spice compatible models
for the MOSFET (level 1-7) and diode are included in this
release.
Since it is fully interactive, it is possible to make changes and
re-simulate quickly. The interactive design makes it well suited
to the typical iterative design process used it optimizing a circuit
design.
Unlike Spice, the engine is designed to do true mixed-mode
simulation. Most of the code is in place for future support of
event driven analog simulation, and true multi-rate simulation.
If you are tired of Spice and want a second opinion, you want to
play with the circuit and want a simulator that is interactive,
you want to study the source code and want something easier to
follow than Spice, or you are a researcher working on modeling
and want automated model generation tools to make your job easier,
try GnuCap.
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Gerber Viewer (gerbv) is a viewer for Gerber files. Gerber files
are generated from PCB CAD system and sent to PCB manufacturers
as basis for the manufacturing process.
The different layers of the PCB are separated into different files.
gerbv can load all files at the same time, though it can not show
them at the same time. You have to browse through the different layers
with the radio buttons on the right side.
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redefines about which buildlink.mk files would care is BUILDLINK_X11_DIR,
which points to the location of the X11R6 hierarchy used during building.
If x11.buildlink.mk isn't included, then BUILDLINK_X11_DIR defaults to
${X11BASE} (set in bsd.pkg.mk), so its value is always safe to use. Remove
the ifdefs surrounding the use of BUILDLINK_X11_DIR in tk/buildlink.mk and
revert changes to move x11.buildlink.mk before the other buildlink.mk files.
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changes since last snapshot include:
- addition of a fpga target for synthesis. outputs edif, optimized for
xilinx virtex parts.
- fixed bug with synthesis of !=
- fixed bug in hex constant parsing
- fixed vvp bug with subtracting very wide words
- much improved VCD output
- many other bug fixes and robustness improvements.
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use X11_BUILDLINK_MK as a test value. Generally just reordering the
inclusions so that x11.buildlink.mk comes before the other buildlink.mk
files will make everthing work.
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New in 20011020:
- better measurement: value at both cursors or difference in values at cursors
- enhanced handling of log scales
- yet more file-reading improvements and general bug fixes
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foo-* to foo-[0-9]*. This is to cause the dependencies to match only the
packages whose base package name is "foo", and not those named "foo-bar".
A concrete example is p5-Net-* matching p5-Net-DNS as well as p5-Net. Also
change dependency examples in Packages.txt to reflect this.
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WRKSRC= ${WRKDIR}
This is much cleaner, much more indicative of what happens, and removes
another of the negative definitions (NO_.* = value).
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Changes include:
- add the ability to specify gain in terms of voltage gain _or_ power gain
- add input/output resistance keywords
- add defaults keyword to allow users to change program defaults on the fly
- the cascade-mode for emacs now works for fontlock
- add voltage output levels in addition to the power levels
- add a verbose style comment (ie, one which gets copied to the output file
instead of being simply ignored).
- new homepage and master ftp site.
The previous version had no known bugs. Hopefully this one won't either.
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to ${X11BASE} in the header and library search paths into references to
${LOCALBASE}/share/x11-links. These packages should now be strongly-
buildlinked regardless of whether xpkgwedge is installed.
Changes well-tested on NetBSD-1.5X/i386 with and without xpkgwedge and
lightly-tested on NetBSD-1.5.1/alpha without xpkgwedge.
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bsd.prefs.mk so that it is actually used. Where possible, include
xaw.buildlink.mk instead of setting USE_XAW, and use LIBXAW where needed.
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* The Big Change: VVP
Past versions of Icarus Verilog performed simulation by compiling the
Verilog design to intermediate C++ code, then in turn compiling that
C++ (usually with G++) to a binary executable. This program was then
executed to actually run the simulation.
The 0.5 compiler, however, uses a custom internal language called
"vvp." The vvp code generator writes a program in the vvp language
that the vvp interpreter executes. This gets runtime performance
similar to the older vvm method, but compile times are much faster.
The result of this change is that there is a new program, ``vvp'',
that is installed with the existing ``iverilog'' compiler. This
program actually executes the simulation generated by the vvp code
generator.
There are manual pages for the iverilog command and the new vvp
command, as well as a QUICK_START document to help you run your first
simulation.
* What Else Is New
The compiler itself is now a lot more robust. While it still does not
compile and understand the entire IEEE1364 standard, the compiler is
less likely to crash on bad input, gives better error messages, and
has generally been cleaned up.
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this represents nearly a year and a half of bug fixes and enhancements to
numerous to list here.
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adds many many more parts and fixes some bugs.
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this represents nearly a year of bugfixes.
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this represents nearly a year and a half of bug fixes and enhancements
including some additional netlist types.
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this represents nearly a year and a half of bug fixes and enhancements to
numerous to list.
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mostly bugfixes to address compiler warnings.
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brings the documentation more in line with the programs.
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This represents nearly a year and a half of bugfixes and enhancements too
numerous to list.
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------------------
ACS 0.29 release notes (06/30/2001)
The primary effort has been to implement IBIS, which is still not
done. The changes here are mostly infrastructure changes needed to
support IBIS.
New features:
1. "Fit" function has choice of fit order and extrapolation. You can
have order 0, 1, 2, or 3.
2. "Posy" has even and odd options, to determine what happens in the
negative region.
3. Modelgen improvements. It now is useful for the whole device,
sometimes. It now handles probes and the device side of the model.
The diode uses it completely. There are still a few missing features
needed for the MOSFET and BJT.
4. Spice-3 compatible semiconductor resistor and capacitor.
5. "Table" model statement.
Improvements, bug fixes, etc.
1. Option "numdgt" really works.
2. Better error messages from modelgen.
3. Code changes for optimization of commons. This should reduce
memory use, sometimes, by sharing commons. Common sharing is still
not fully implemented.
4. Fix two bugs that sometimes caused problems after a "modify" or on
a "fault".
5. Better handling of "vmin" and "vmax". It should be much less
likely that limiting causes convergence to a nonsense result.
Some things that are still partially implemented:
1. Internal element: non-quasi-static poly-capacitor.
2. BSIM models, charge effects, "alpha0" parameter. (computed then ignored)
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changes are:
-----------
RELEASE NOTE FOR ICARUS VERILOG 20010630
I've done some cleanup of the mingw port of Icarus Verilog. I've also
added instructions for how to build Icarus Verilog under mingw. I'm
working on making that the preferred way to support Windows, and when
I make the 0.5 release I will make Windows binaries this way. Anyhow,
feedback on the build instructions and the build results using the
instructions in mingw.txt are welcome.
I've make "vvp" the default target type. The older vvm behavior is
available with the "-tvvm" flag to iverilog, but I would rather be
told about (and fix) bugs in the vvp code generator and run time.
I've added support for the (unsigned) right shift operator. The left
shift has been working for a while now, but right shift somehow
slipped through the cracks. The shift operators still don't quite work
in structural contexts, but they should show up sometime next week.
I've finally got VCD output working properly with vvp. It may even be
better then with vvm, although some internal symbols are still generated.
A few odd bugs have been fixed, including a code generation error for
xnf, and error checking of user defined function parameters.
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bump to nb1.
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