| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
+ move the patch digest/checksum values from files/patch-sum to distinfo
|
|
|
|
changes since last snapshot are (from the authors email)
verilog-20010407
--------------------
Still more progress on the new VVP simulation engine:
As with last week, this snapshot includes a lot of work on the ivl_target
API in support of code generation for vvp. Also, the vvp execution engine
has progressed some.
In fact, vvp has grown up to understand signed vectors and some signed
expressions. The signed vectors are mostly for VPI use, the signed
comparison instructions actually do signed work. Case comparisons are
new, along with %and and %or instructions, and %nor/r for reduction.
I also added a few new gate types to the .functor support.
A bug in the propagation of values by %set instructions has been fixed.
Specifically, the %set instruction not only sets the value of the .var
that it references, but also executes the propagation events that result.
This fixed some event ordering bugs.
Some VPI support needed by system.vpi is added to vvp to allow it to
properly handle signed signals, decimal values, and a few other details.
$display should work much better then it did last week.
Back in the vvp.tgt code generator, lots of new stuff is happening.
Several of the bitwise binary operators have been added, as well as
more comparison operators. This includes handling of signed expressions.
This also implies that vvp.tgt generates the proper .net vs .net/s
and .var vs .var/s statements.
User defined functions and tasks are now working. In fact, the vvp
target probably handles more functions (in behavioral code) then the
vvm engine. I've received several bug reports about user defined functions
with loops, that don't work under vvm. These should work with vvp.
Non-blocking assignments now work, too.
All forms of case/casex/casez are supported by the code generator, and
use the proper compare instructions. Forever, Repeat and While loops
also work now. A few bugs in event handling, and all the edge types
(including behavioral triggers) should work with limitations. Event or
is still in the works, and any-edge of large vectors (>4 bits) does not
work.
*Whew!*
As you can see, a *lot* of stuff is happening. I'm up to passing 110+
tests in the regression test suite (Icarus Verilog/vvm passes 318 tests)
so the changes are actually making things work. Test and be merry!
verilog-20010331
--------------------
More and more progress on VVP. More and more snapshots.
A lot of work has been done to the ivl_target loadable target API.
This API is growing to support the also growing tgt-vvp target. I've
added support for case statements, event triggers fork blocks.
Of course this also means that the tgt-vvp code generator and the
vvp simulator now support constructs including case, events, and
parallel blocks.
I've also fixed up the driver to properly report errors that tgt-vvp
detect. This makes the test suite regression script work a lot better.
I'm up to more then 70 tests in the test suite passing. I'm finding
that writing the code generator for vvp assembly is a *lot* easier
then writing a code generator for C++/vvm. Fortunately, the vvp
assembler is pretty fast.
At any rate, the vvp simulation engine is starting to show signs of
being useful. It still does not cover nearly as much of Verilog as
vvm, but what it does cover is so much faster that it may be worth
your while to try it out. And more eyes looking at it can only be a
good thing.
|
|
|
|
|
|
the authors announcement are:
There are a few bugs in the main compiler that are fixed. There has
also been an extension to the $fopen that adds support for opening
files for reading. The $fgetc has been added to take advantage of this.
This was done on the VPI side, although a slight extension to the mcd
functions was created.
The real news is the vvp simulation engine. I've added the tgt-vvp
code generator source and the vvp assembler/simulator, and the combination
actually produces the occasional working program. And it makes them
very quickly. So far as I can tell now, I am going to be very pleased
with the final outcome when this work is complete. However, it is not
at all ready to use. This snapshot is mostly to give a preview of things
to come to a wider audience.
HOW VVP WORKS
If you are accustomed to the existing vvm behavior, you remember that
the vvm simulator works by generating C++ and feeding that to the g++
compiler. Many of you are painfully aware of that.
VVP does *not* work like that. Instead of generating C++, the
generator emits assembly language for an abstract simulator processor.
The processor that the assembly targets doesn't really exist, but the
vvp program, included in this Icarus Verilog snapshot, assembles the
code to data structures in memory, then efficiently emulates the abstract
processor.
So the simulation of a program via vvp works by first compiling the
Verilog to vvp assembly. The vvp.tgt modules generates the code, and
is envoked when you use the ``-tvvp'' switch to iverilog.
The vvp assembly file so created is then passed to the vvp program to
be assembled and executed. There is a single vvp input file that is the
design to simulate. The vvp assembler is designed to execute the design
efficiently.
HOW TO LEARN MORE
The ivl_target.h header file describes the loadable target API that
the vvp code generator uses to gain access to the design. Then the
tgt-vvp directory contains the implementation of the vvp code generator.
The vvp directory contains the implementation of the assembler/simulator
that runs the compiled design. The README.txt file describes how the
vvp program works in general, and points to other txt files. There are
a variety of other .txt files in the vvp directory that describe how
the major components of the vvp program work.
|
|
first component is now a package name+version/pattern, no more
executable/patchname/whatnot.
While there, introduce BUILD_USES_MSGFMT as shorthand to pull in
devel/gettext unless /usr/bin/msgfmt exists (i.e. on post-1.5 -current).
Patch by Alistair Crooks <agc@netbsd.org>
|
|
|
|
QCad is a simple 2D CAD System. With QCad you can easily construct and
modify drawings with ISO-texts, dimensions, hatches and many other
features and save them as DXF-files. These DXF-files are the interface
to many CAD-systems such as AutoCAD and many others.
|
|
While here, update MASTER_SITE.
changes from last packaged version:
* Changes in Dinotrace 9.1b 2/13/2001
**** Documentation updates.
* Changes in Dinotrace 9.1a 1/22/2001
** Added analog waveform format. [Dave Colson]
Includes new Signal Waveform menu and signal_waveform command.
* Changes in Dinotrace 9.0m 11/21/2000
**** Fixed a bug reading compressed tempest on Digital UNIX. [Steve Hoover]
|
|
|
|
|
|
While I'm here, unify category Makefiles to more standard style.
(If you have tools depending on the previous form, please fix them.)
|
|
|
|
|
|
some 64 bit related compiler warnings to fix.
- while here, use libffm if on an alpha for faster math. In this case
20-30% faster.
|
|
up a possibly out of date installed header from ${LOCALBASE}/include.
Note that while we don't support installing a pkg when a previous version
is installed, we should still be able to build it.
Problem noted in private email from Lennart Augustsson.
|
|
|
|
|
|
from the authors announcement:
So many things have changed since version 0.3 that there is no point
in listing them. There have been tons and tons of bug fixes and the
language coverage is better, and so on and so forth. It's just so very
much better then version 0.3:-)
speaking as a user, some of my personal favorites are:
- support for signed variables
- iverilog now gives correct return codes (which makes 'make' much happier)
for a more complete list, the commit messages for
pkgsrc/cad/verilog-current/Makefile contain the changes for each
development snapshot between verilog-0.3 and verilog-0.4
|
|
considered stable. Xcircuit now has the ability to pass parameters
to objects. For the moment, this only works with string parameters.
Integral parameters will be added in upcoming versions.
|
|
bug fixes and signed support (yay!).
detailed changes since last packaged snapshot from the
authors announcements:
Icarus Verilog snapshot 20010113
--------------------------------
We're getting close to release candidates. Maybe another snapshot, then
I start with making 0.4 release candidates. So lets get this tested so
that I can move forward!
This snapshot largely fixes a whole bunch of bugs. I'm working feverishly
to catch up to the reported bugs, but they are coming in about as fast
as I can resolve them. (Not that I'm complaining, mind you. These PRs
are really helping me make it better.) But that means I'm going to just
concentrate on getting as many PRs done as I can before the release.
The syntax of functions and tasks has been expanded to allow parameters.
This is not a common thing to do, but someone puts parameters if functions
The syntax of functions and tasks has been expanded to allow parameters.
This is not a common thing to do, but someone puts parameters if functions
so I had a PR to fix:-) Also I caught a problem with executing functions
that take no input parameters. In fact, a bunch of function related bugs
were fixed. I lost track of em all.
Ports of tasks weren't elaborated properly. I fixed this and a few related
problems so most legal l-values should work as task port expressions now.
Memories within tasks should also work properly now.
Speaking of ports, I now report errors when there is a port direction
for module ports that don't exist. In fact, there are a whole bunch of
cases where I've added required error messages.
The %d format of display strings now displays signed negative values as
negative values instead of the unsigned equivalent. This goes along with
the other signed arithmetic features from the -2000 standard that are now
supported.
I fixed up the Makefiles (thanks to a contribution) to support build using
the VPATH capabilities of the makefile. You should be able to compile for
multiple targets now from a shared source directory.
Icarus Verilog snapshot 20010106
--------------------------------
I'm just managing to barely keep up with the bug reports arriving in
the bug tracking system. I'm pleased with the success of the ivl-bugs
robot. These bug reports have allowed me to better manage and record
progress. Keep those bug reports coming!
I've added support for arrays of integer and time variables, as well
as the Verilog 2000 initialization syntax for these types. I have also
made some internal changes to integer support. Integers are now just
a shorthand for ``reg signed [31:0]'' and signed variable support has
made some internal changes to integer support. Integers are now just
a shorthand for ``reg signed [31:0]'' and signed variable support has
been generalized. This makes it easier on the code generators, as they
do not need to know that a variable was a integer, a time, a foo or a bar.
I few constant propagation errors have been fixed. Continuous assignments
of constants to nets should behave correctly now.
Many people noticed lack of expression support for parameters. In fact,
the problem was a lack of support for a bunch of specific operators. I've
added many operators. This has the side effect of improving constant
propagation as well, in some cases finding more dead code to eliminate.
This also affected expressions that were index expressions of memories
and vector declarations.
The / operator in continuous assignment expressions is fixed. There were
a few size related issue here that are now fixed.
I've added to the i3331364-notes.txt file a clarification of my position
on parse of repeat statements. This position is compatible with XL behavior.
Passing parameters to user defined functions in behavioral code was pretty
darn broken. I managed to fix this. You can tell that not many people use
user defined functions:-) (It doesn't help that Icarus Verilog is picky
about them.)
For vvm, I've put some effort into optimizing the compile time of programs
by reducing the size of the output code. I've reduced redundancies some,
and used loops to handle vectors where possible.
A few bugs related to $dumpvars were cleaned up. Function scopes work.
|
|
out of date - it was based on a.out OBJECT_FMT, and added entries in the
generated PLISTs to reflect the symlinks that ELF packages uses. It also
tried to be clever, and removed and recreated any symbolic links that were
created, which has resulted in some fun, especially with packages which
use dlopen(3) to load modules. Some recent changes to our ld.so to bring
it more into line with other Operating Systems also exposed some cracks.
+ Modify bsd.pkg.mk and its shared object handling, so that PLISTs now contain
the ELF symlinks.
+ Don't mess about with file system entries when handling shared objects in
bsd.pkg.mk, since it's likely that libtool and the BSD *.mk processing will
have got it right, and have a much better idea than we do.
+ Modify PLISTs to contain "ELF symlinks"
+ On a.out platforms, delete any "ELF symlinks" from the generated PLISTs
+ On ELF platforms, no extra processing needs to be done in bsd.pkg.mk
+ Modify print-PLIST target in bsd.pkg.mk to add dummy symlink entries on
a.out platforms
+ Update the documentation in Packages.txt
With many thanks to Thomas Klausner for keeping me honest with this.
|
|
headers and libraries.
fixes recently noted compile problems seen by Huberts bulk i386 builds.
|
|
|
|
|
|
|
|
Changes since the last packaged snapshot are (from the authors announcements):
Icarus Verilog snapshot 20001216
--------------------------------
This is the last snapshot before the holidays, so I hope it has your
favorite present in it. A lot of PR#s have been dealt with, and for a
brief moment I felt like I was getting ahead of the pending list:-)
I've added support for non-integer times, at least in a few contexts.
The `timescale directives should interact properly with the decimal
point in delays, causing more accurate timing simulations. This should
make vendor-supplied libraries work much better.
I've added support for signed reg variables. Signed expressions should
now generally do the right thing, but this feature needs much more testing,
and many more tests in the test suite. However, I do know that signed
comparisons should work properly. Bug reports for problems with signed
arithmetic are encouraged.
Many people have been having troubles with Cygwin compilation. The
problem was with the latest version of binutils. Venkat came up with a
solution that works with old and new binutils, so you can now compile
with the very latest cygwin software. This should make things a lot
easier for a lot of people.
I've made initial steps toward an HP/UX port. The configure script should
detect the right dl library to use, and the t-dll target should be able
to load loadable targets. I am looking for a volunteer to take responsibility
for the HP/UX port as I have no suitable machines. Said person should
be able to compile Icarus Verilog, manage HP/UX specific portability
issues, and be able to make precompiled packages when the stable release
is out.
I'm still looking for a similar volunteer for FreeBSD/{alpha,i386}.
Some more progress was made on support for PALs. I'm close to choosing
macrocell modes and configuring fuses. Won't be long now, folks.
Icarus Verilog snapshot 20001129
--------------------------------
few more constant propagation improvements this time, most notably
XOR an XNOR are now fairly complete. These are interesting as they are
generated by comparison operators so show up pretty often. And it is
common to compare numbers to constants. Thus, there are lots of oppor-
tunities for gate elimination!
Synthesis of unary ! now works. Unary ~| (reduction nor) should also
be in good shape now, as should binary || (logical or). Synthesis of
binary && is still a little shaky. Go ahead and file reports if you
trip on it. Binary != was broken with XNF synthesis, so that is also
fixed, along with a few cases of mangled XNF output. And there were
also a few bugs related to the CE of inferred DFFs, that didn't get
connected.
A *big* problem with synthesis occurred with non-blocking assignment.
Icarus Verilog simply failed to synthesize the r-value of the assignment
and all kinds of bad things happened. I fixed this, it's better now.
Whew! Lots of XNF synthesis bugs fixed! This is what happens when users
take the time to submit good bug reports.
There are also some bugs related to dead signal elimination that causes
Icarus Verilog to crash in some synthesis cases. These have been fixed
up so far as I know.
I have slightly improved root module detection of iverilog. If there is
only one module in a source file, it is pretty obvious that it is the root
module, even if it has ports. This is a common case for XNF synthesis
(especially when making small macros with Icarus Verilog) and should save
some typing and confusion.
|
|
|
|
|
|
-all previous netbsd patches have been incorporated (Thanks Steve!)
-changes from the authors announcement:
I fixed a problem with some systems not having getopt.h. I forget
which system it was, but configure takes care of it. I've also fixed
some broken install targets in the Makefiles.
I've added a new pin_count statement to PA files, so that the library
can provide to the user more information about the pinout of the device
in question. Applications may use this to help manage its pin binding
tasks.
A contributed 16l8 part description file was contributed, and included
in this release.
|
|
postscript manual.
|
|
Consistent 4 character indentation of SUBDIR entries.
|
|
|
|
|
|
|
|
|
|
Free system for introductory level finite element analysis
|
|
* A new part: wire jumper.
* Drag'n'drop from the part preview to place parts.
* A crude form of auto numbering when placing parts.
* Cleaned up makefiles and put some samples in
*<prefix>/share/oregano/samples/.
* Changed default spice executable name to spice3.
* Connection dots.
* A simple voltmeter function.
* Fix various ref/unref/sink design flaws, to
increased stability.
* Part browser remembers the previously selected part
when switching libraries.
* Should really work with libxml 2.x this time... :-)
* Reorganization of installation directories for model
and library files.
* The plot widget now features axis values.
* New parts: uA741 opamp and a simple zener diode.
* Parts and wires can be flipped horizontally and vertically.
* Enabled loading of simulation settings again.
* Added a simple text label item to put text on the sheet.
* Fixed the 'sometimes non-disappearing floating item' bug.
* Should now also work with libxml 2.x (untested).
* Switched C and B on the BJT transistor models.
* Removed the unfinished printing support for now.
* Redesign of lots of internals.
* Added lots of functionality to the parts library,
such as model files, and conditional values in templates.
* Improved a few of the icons.
* Fixed a bug where the name of the markers could not be edited.
* You can inspect the connection span, by holding Control while
moving the cursor over wires.
* Added the ability to rotate parts while placing them; press 'r'
to achieve this.
* Logging of Spice warnings and errors during simulation.
The messages can be shown in a log window.
* Beautification of the part browser UI.
* Added more tooltips and updated some translations.
* Fixed a few non-critical bugs.
* New and improved part properties editor.
* Improved user interface for the plot window.
* Internationalization fixes to netlist generation
and schematic loading/saving.
* The simulation now uses the user supplied time step size.
* French translation from David Monniaux.
* Even more refinement of the default library symbols/parts.
* Mission 'Code Cleaning' continues.
* Cut/copy/paste is implemented.
* The symbols are redrawn to look much nicer and more standard.
* Some new symbols, e.g. MOSFETs.
* There can be more than one part library, thanks to Elker Cavina.
* A bug with simulation time settings was fixed.
* There is a problem with some spice packages, that make them generate
binary output, even though the default should be ascii. This is now
fixed by telling spice to always output text.
* The help files are now installed in the rpm package.
* Lots of code restructuring and cleaning.
|
|
don't know what happened the first try.
|
|
changes since the last packaged version (from the authors announcements):
Icarus Verilog snapshot 20001119
--------------------------------
The big change here (code wise) is improved and corrected constant
propagation. I was missing OR, NOR, NAND and XOR propagations, and
got some of the AND calculations wrong. This fixes this shortcoming
and in some cases this actually may speed up your compile a tiny bit.
Some more dangling signals are also eliminated.
supply nets are now working (PR#17). They also will trigger constant
propagation (as they have constant values) in certain cases.
Those of you doing cygwin compiles have trouble compiling parse.cc. I've
put into the cygwin.txt some slightly better instructions for dealing with
this situation, when it comes up.
I've also added missing symbols to ivl.def, so that tgt-stub properly
links.
Icarus Verilog snapshot 20001112
--------------------------------
This snapshot includes support for MOS et al devices as contributed
by Tim Leight. It appears to actually work as advertised, and I also
have from him a collection of tests that I'll be adding to the test
suite as soon as I get copyright information from him. So if you have
been dreaming of simulating MOS devices with Icarus Verilog, give this
a try. This update also fixed PR#27.
I've also cleared up a few bugs related to unconnected module ports.
Module port syntax is pretty byzantine, as PR#38 shows.
The loadable target API has gained access to flip-flops. This is required
for PLD code generation to work. I think the ivl_target API now supports
the minimum devices needed to generate PLD files, and I'm on to the task
of getting ancillary PAL support working.
Icarus Verilog snapshot 20001104
--------------------------------
Yes, I've managed to find the right bits to get Icarus Verilog to compile
on RedHat 7.0, and this snapshot includes those fixes. It took some back-
and-forth with tech support at RedHat to get it going.
I've also fixed up make check so that it works in general. If you use
"make check" after building, the makefile will run the examples/hello.vl
program through the local parts to make sure they minimally work.
I've added support for the "time" data time and more complete support
for the $time system function. These should work properly in all cases
now, so cases of not working are worthy of a bug report.
I've also integrated a re-implementation of sequential UDPs from Stephan
Boettcher, so I would appreciate it if all you folks using primitives
give this a fresh test. (It should be an improvement.)
This is a relatively small message, which doesn't reflect the complexity
of the changes. The "time" support in particular caused a lot of threads
to be pulled. Also, I've been doing some PLD stuff on the side, so I've
been busy.
I've also knocked of PR#11, 14, 33, 34, 39 and a few other bugs.
|
|
changes (from the announcement):
The libipal library has gained access to more structural information
about the device, including enable SOPs. It is also now possible to
lookup a SOP by name and by pin. Also, access to sop fuse positions
has been improved.
The toplevel makefiles were changed to use $(MAKE) instead of make.
There are a few other niggling makefile fixes as well.
ipalrev and ipaledit now both take the -p flag allowing you to choose
the architecture for your device, and there are now two devices to
choose from. (both 22v10s:-)
ipalrev was seriously confused about inversions and the sense of things,
but that should be all cleared up now. It does a decent, if not complete,
job of decompiling 22v10 designs.
And finally, the PA file format has been extended to accommodate the
new library features, and PA files are now named according to a naming
convention for identifying devices.
|
|
from the NEWS file:
New in 20001123:
- Saving wave and panel configuration as guile scripts.
- Executing guile scripts from menu or command line (-s <script> option)
- Remote control using the gwave-exec and gwaverepl utilities
New in 20001004:
- Spice3/Ngspice rawfile improvements: binary files now work!
- Other minor file-reading improvements.
- spice source code to examples for which I could still find it.
New in 20001004:
- Major improvements to handling of binary files produced by HSPICE.
- Overhaul of input of spice3/ngspice raw files; more robust and tolerant
of complex numbers.
- User interface improvements: tooltips added. User's .gwaverc no longer
required to do lots of standard setup. system.gwaverc can be copied
to $HOME/.gwaverc and edited to taste.
- sp2sp utility included for converting any spice file readable by gwave into
a convenient tabular ascii format.
|
|
from the NEWS file:
* Changes in Dinotrace 9.0l 8/30/2000
** Added support for femtosecond Verilog timescales [Derek Bosch]
|
|
from the history file:
----------------------
New features:
1. New probes: diode G, mos IBD, IBS, GBD, GBS.
2. New options: "floor" and "vfloor". (Floor was in the manual, but
not in the simulator.)
Improvements, bug fixes, etc.
1. There is a change to the way behavioral modeling conditionals are
handled. It should now be 100% compatible with SPICE, considering the
subset that duplicates SPICE. There are still significant extensions
beyond SPICE, particularly that you can have behavioral resistors,
capacitors, inductors, etc.
2. Parameter default calculations are now done in a manner consistent
with Spice 3f5. Previously, it was supposedly consistent with Spice
2g6.
3. A bug in calculation of threshold voltage of the level 6 model, for
P channel devices, has been fixed.
4. A bug in calculation of Meyer capacitances when the device is
reversed has been fixed. This bug sometimes caused a discontinuity at
vds=0.
5. I have added some smoothing to the Meyer mos capacitor models.
This improves convergence. The down side is that sometimes the
answers are different. It is probably a little better, when
considering closeness to reality, but it is still Meyer's model.
6. MOSFET parasitic diodes are now the same as those used in Spice.
7. There are subtle changes in the diode model. I think this usually
improves convergence.
8. Charge calculation in Meyer capacitors and diode capacitiors is now
supposedly Spice 3 compatible.
9. An error in BSIM3 scaling has been fixed.
Some things that are still partially implemented:
1. Internal element: non-quasi-static poly-capacitor.
2. BSIM models, charge effects.
Bugs (nothing new, but needs repeating):
1. The transmission line initial conditions are not propagated until
the transient analysis runs.
2. The makefile does not set up the proper link for the model
compiler. You need to do it manually.
3. A bad setting of "vmax" and "vmin" can lead to convergence to a
nonsense result. It is not as bad now as it used to be.
|
|
|
|
|
|
note, this is the development snapshot version of the package. As stable
releases become available, there will be a ipal package.
from DESCR:
Icarus PAL is a set of libraries and utilities for manipulating PAL
designs. The design information is conveyed in the industry standard
JEDEC file format.
Icarus PAL accepts parts descriptions that detail the device
structure, capabilities and pinouts so that software can be written to
work relatively independent of the part type. These parts descriptions
also describe how the fuses of a device are arranged, so that
synthesis tools can generate fuse maps to get the desired
functionality and pinout. See as a commented example the description
in the pa/pal22v10.pa description.
The ipaledit program takes as input a .JED file and displays the PAL
design. It shows the sum-of-products as a fuse matrix, and shows the
macrocell configurations in convenient form.
The ipalrev program takes as input a .JED file and reverse compiles
it, producing a Verilog program that logically describes the
design. This use useful for moving old designs to new tools.
Please note that this package is a development snapshot and while it contains
the latest and greatest features, it may be buggy as well. When
available there will be a seperate ipal package which will be made of
the stable releases.
|
|
|
|
from DESCR:
The program is a viewer and editor for:
-GDSII files, KEY files (own made extended GDSII in ascii format) and
DAVID MANN files (flash format for mask plotting)
Features:
-It allows to draw primitives on a chosen layer, and to manipulate them.
-stack oriented tools allows zooming while drawing new primitives and
editing them. This also makes it possible to draw extremely accurate.
-primitives on the layers or/can be transparent colors and fill patterns
can be set on a layer basis
-drawing order of layers can be changed
-a hiearchy of pictures, named structures, can be handled and manipulated
-saving as a bitmap and other formats.
-measuring distances
-adding user defined properties to primitives
-boolean OR AND EXOR A-B B-A
-positive and negative process offset
-circle recognition in polygon and polyline data.
-move copy delete etc.
-transformations (scaling , rotation , moving)
-flatten the hiearchy of the drawing
-drivers for CNC (laser and milling machinery)
|
