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the assembler on pmax (1.4.1) to never complete.
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- Make sure -Rpath is done correctly
- Make sure qt libs are found
- Make sure -lz -lpng -lSM are included as libqt needs functions
from these libraries.
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the previous pkg was based on a development version of vipec. This version
is considered a stable release.
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components. This allows users of Qt to specify QTDIR=/path/to/qt instead
of having to patch all configure scripts and makefiles to look for alternate
names. This is the recommended approach from Troll Tech (Qt authors).
update pkgs which use qt1 to reflect this.
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New features:
1. BSIM1, BSIM2 models -- DC only.
2. New elements:
trans-capacitor
voltage controlled capacitor
voltage controlled conductance
voltage controlled resistor
3. Optional new syntax, with type first so component labels can start
with any letter, and the choice of components is no longer limited by
the 26 letters. This was necessary for a clean syntax
for #2.
4. Some new parameters on existing devices, also a side
effect of the BSIM work.
5. The manual in HTML form. The manual source is still in LaTeX,
which can be used to generate HTML, PDF, Postscript, or many other
formats.
Bug fixes:
1. An error causing truncation error to be underestimated has been fixed.
Other improvements:
1. MOSFET model evaluation is a little faster, due to use of one of
the new elements to replace several old ones. I have seen 40%, but
20% is more likely. The improvement is most evident on busy circuits,
where the ACS speed enhancements based on latency exploitation
contribute more overhead than their value, that is .. the type of
circuit that has run faster in Spice than ACS.
2. More documentation on internals.
Changes that I think are improvements, but some may disagree:
1. Truncation error based step control is disabled when Euler's method
is selected. The justification for this is that the reason for
selecting Euler's method is to avoid the artifacts of high order
methods on "stiff" poles. Without this change, a "stiff" pole would
cause an unreasonably small step size. This did not appear to be much
of a problem in the old release because the use of an incorrect
formula for estimating truncation error. A "stiff" pole is one that
has a response so fast it can be thought of as instantaneous.
2. The "help" command, with its 4 year old help file, has been
removed. The concept is really obsolete. With the HTML form of the
manual, a full online manual is a better replacement.
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Notable changes since the last pkg are (from the snapshot announcement):
Parameters are complete.
What this means is that I finally got around to supporting defparam,
and while I was at it I rewrote the entire parameter handling and added
the parameter support included in 1364-2000.
I have rewritten major portions of the VVM backend. The vvm_nexus class
has been introduced to the fray, and all the device implementations in
the VVM library now use the nexus to drive and receive values. An advantage
of this scheme is that the t-vvm backend code (in ivl proper) is simpler,
and so is the generated C++ code.
I also removed most of the template classes. This proved to be a huge
compile-time benefit (though compiling twice as fast really only matters
for large programs) and it doesn't seem likely to hurt run-time performance.
A few remain, either because they seemed harmless (the N-wide logic gates)
or I couldn't yet figure out a good way to replace them (vvm_bitset_t).
A side benefit of this is that the vvm library may now be a modeling
library that ordinary humans can use to write their models in C++. This
may provide the unexpected benefit of heading me towards incremental
compilation of designs. So who was it who was beating me over the head
asking for that?-)
I also fixed a few minor problems with the preprocessor. Those of you
who reported problems with `includes and `defines should check this out.
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Dinotrace is a tool designed to aid in viewing Verilog Value Change
Dump (.vcd), ASCII, Verilator, Tempest CCLI, COSMOS, Chango and Decsim
Binary simulation traces. It is optimized for rapid design debugging using
X-Windows Mosaic.
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of the cad/verilog package. Development snapshots are created quite frequently
in between stable releases.
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verilog-current pkg to track development snapshots.
This version has minor bug fixes over the previous snapshot package. Notable
$display of a memory element now works correctly and a bug in $readmemb has
been fixed.
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Gwave is a viewer for spice-like simulator output and other analog data
Gwave can read several file formats. It attempts to guess file formats
based on filename, and then tries all file formats until one succedes.
These file formats are known:
CAzM transient output (*.[BNW])
HSPICE binary and ascii formats (*.tr0, *.sw0, *.ac0)
Spice2 and Spice3 "raw" output (*.raw)
An ascii format with whitespace-seperated columns and column headings,
such as that produced by ACS (Al's circuit simulator). (*.acs, *.asc, *.ascii)
The "Export Postscript" and "Export PNM" options on the main File menu
provide the rudiments of output for inclusion in other
documentation. They and simply write out files called gwave_out.ps and
gwave_out.pnm into the current directory. In the future, a dialog box
will allow configuring the print and export output.
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converted from FreeBSD, or have been disabled since. Sorted lines
alphabetically, added some missing directories.
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Changes include:
* New dialog boxes by Matt Ettus:
- A much improved attribute edit dialog box
- A multiple attribute edit dialog box
* Improved Hierarchy Support:
- Hierarchy/Down Schematic
- Hierarchy/Down Symbol
- Hierarchy/Up
* Text alignment.
* Attributes are now required to have no spaces besides
the equals sign on each side. This shouldn't cause
any problems for anybody.
* Bunch of updates to the various gnetlist backends
(basically all submitted changes have been integrated).
Integration of JM Routoure's PCB backend work (Thanks!).
Bug fixes and improvements by Matt Ettus, Stefan
Petersen and Bas Gieltjes.
* Added a bunch of contributed symbols. Thanks to
all that have contributed! There are now 566 symbols
in the library.
* Documentation. There are the beginnings of docs now.
Here's the current list:
attributes.txt -- Master attribute list
fileformats.html -- gEDA file formats
gschem.txt -- The start of a serious user's
guide keymapping.html -- Stefan's keymapping
document netattrib.txt -- A HOWTO on the net=
attribute symbols.html -- The ever useful symbol
creation guide
* Bug fixes and improvements to some of the utils.
* Lots and lots of bug fixes (and bug introductions).
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simulation of electrical circuits
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NetBSD pkgsrc patches to the previous release. Thanks to Stephen Williams
(the author) for his willingness to accept patches!
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Cascade is a program for analyzing the noise and distortion
performance of a cascade of elements in an electronic system. A
typical application of cascade is the analysis of a receiver. A text
description of the receiver block diagram consisting of things like
amplifiers, mixers, and filters is entered into cascade. Each element
is characterized by its gain and optionally noise figure, and third
order intercept point. The program then analyzes the system and
produces a report detailing the performance at each stage.
A summary is produced which shows the relative contributions to the
total system performance of each block. This allows easy
identification of what limits system performance.
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Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
compiler, compiling source code writen in Verilog (IEEE-1364) into some target
format. For batch simulation, the compiler can generate C++ code that is
compiled and linked with a run time library (called "vvm") then executed as
a command to run the simulation. For synthesis, the compiler generates
netlists in the desired format.
The compiler proper is intended to parse and elaborate design descriptions
written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
complex standard, so it will take some time for it to get there, but that's
the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well,
and some -1999 features will creep in.
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ACS is a general purpose circuit simulator. It performs nonlinear
dc and transient analyses, fourier analysis, and ac analysis
linearized at an operating point. It is fully interactive and
command driven. It can also be run in batch mode or as a server.
The output is produced as it simulates. Spice compatible models
for the MOSFET (level 1,2,3,6) and diode are included in this
release.
Since it is fully interactive, it is possible to make changes and
re-simulate quickly. The interactive design makes it well suited
to the typical iterative design process used it optimizing a circuit
design. It is also well suited to undergraduate teaching where
Spice in batch mode can be quite intimidating. This version, while
still officially in beta test, should be stable enough for basic
undergraduate teaching and courses in MOS design, but not for
bipolar design.
In batch mode it is mostly Spice compatible, so it is often possible
to use the same file for both ACS and Spice.
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enhancements. Most notably, gEDA was split into several independent
modules, using a common library 'libgeda'. These modules are now separate
packages with geda now becoming a meta package.
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gEDA.
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gEDA.
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