Age | Commit message (Collapse) | Author | Files | Lines |
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XXX: I have to check vtk*'s PLISTs and will do so next, but this
PKGREVISION bump is needed anyway.
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The build script overwrote PATH and didn't see the wrapper scripts
for that reason.
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- add missing -lm (how did this work before?)
- remove one last GNU make-ism since there is a portable way of doing
it
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* Dinotrace 9.3c 1/2/2007
*** Add signed decimal radix. [by Uwe Bonnes]
*** Builds now take place in "obj_dir" to keep them distinct from sources.
**** Fix VCD files with 10 or 100 femtosecond resolution.
**** Fix dinotrace.el complaint about bad verilog-mode.el version.
[Joseph Holtgrefe]
**** Fix core dump when no fonts are available. [Dmitri Belimov]
* Dinotrace 9.3b 3/13/2006
*** Fix line number incrementing in Verilog errors. [Uwe Bonnes]
* Dinotrace 9.3a 6/13/2005
*** Fix too small buttons under openmotif.
*** Fix missing keyboard accelerators under openmotif.
* Dinotrace 9.2b 5/03/2005
*** The default extension for Verilog dumps is now .vcd instead of .dmp.
**** Fix traces containing only real numbers. [Vitor Antunes]
**** Fix segfault when doing signal adds. [Guy Hutchinson]
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* Dinotrace 9.3c 1/2/2007
*** Add signed decimal radix. [by Uwe Bonnes]
*** Builds now take place in "obj_dir" to keep them distinct from sources.
**** Fix VCD files with 10 or 100 femtosecond resolution.
**** Fix dinotrace.el complaint about bad verilog-mode.el version.
[Joseph Holtgrefe]
**** Fix core dump when no fonts are available. [Dmitri Belimov]
* Dinotrace 9.3b 3/13/2006
*** Fix line number incrementing in Verilog errors. [Uwe Bonnes]
* Dinotrace 9.3a 6/13/2005
*** Fix too small buttons under openmotif.
*** Fix missing keyboard accelerators under openmotif.
* Dinotrace 9.2b 5/03/2005
*** The default extension for Verilog dumps is now .vcd instead of .dmp.
**** Fix traces containing only real numbers. [Vitor Antunes]
**** Fix segfault when doing signal adds. [Guy Hutchinson]
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Nelma is a (command line) tool for numerically calculating various
electrical properties of printed circuit boards or similar objects
composed of conductors and dielectrics (however code is optimized for
circuit board-like geometry).
It is currently capable of calculating capacitances between objects -
nets on a PCB. It returns a spice-compatible description of an
equivalent circuit of stray capacitances that can be for example used
for more accurate circuit simulation. Alternatively it can also
produce field data that can be plotted for example with Gnuplot.
Support for calculating resistances existed for a while but was later
removed because it didn't receive much testing.
Nelma is available under the GNU General Public License version 2.
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Release Notes for Icarus Verilog Snapshot 20070227
* Fix some problems with specify block parsing. Detect some cases that
are parsed but not properly implemented yet and issue warnings or
errors. Also fixed a few problems with inertial delay model timing.
* Detect is some cases Verilog source errors that can be better
reported to users. This includes more specific error messages for
certain syntax errors.
* Fix problems with overridden continuous assignments.
* Hide bool types from logic type as far as VPI is concerned, for the
sake of compatibility.
* Fix a variety of code generator expression lifetime bugs that caused
obscure (and wrong) output results in behavioral code.
* iverilog-vpi uses the compiler selected at build time.
* Rework handling of strings to handle escape sequences properly.
* Fix some handling of real values in some expression types.
* Get padding of sized, unsigned numbers when x or z are involved.
* Many, many more misc. bug fixes.
* Add an assert mechinism that improves usefulness of bug reports by
reporting source file line numbers when available.
* Compile fixes, using inttypes.h instead of stdint for portability.
* Various spelling fixes.
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LC is simulation tool for the analysis of the electromagnetic
properties of electrical interconnects. The full three-dimensional
circuit is modeled, so all interactions are automatically included in
the solution. The model can be excited by numerous types of waveforms,
and the transient response measured using common values such as
voltage and current. Circuit parameters such as inductance,
capacitance, and impedance can be derived from the transient response,
and frequency-domain results such as S-parameters can also be
calculated. Far field radiation patterns can be obtained.
LC is primarily an electromagnetic simulation and uses the
Finite-Difference Time-Domain (FD-TD) technique. FD-TD is a full wave
explicit solution of Maxwell's equations in three dimensions. In FD-TD,
the rectangular volume enclosing the model is discretized into a large
number of small cells, which may be uniformly-sized, or may vary in size
within the simulation space. The dielectric, permeable, lossy, and
conducting material properties of each cell are incorporated into the
field updates, which are performed iteratively in small time steps.
An interface between the electromagnetic simulation and the circuit
simulation program SPICE is available within LC. This allows the user
to add arbitrary SPICE circuits, such as drivers and loads, into the
interconnect model. The interconnect performance is calculated using
FD-TD while the lumped-element circuits are evaluated by SPICE.
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version 6.9
Update for wxWidgets 2.6.2
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Patch provided by Sergey Svishchev in private mail.
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From Sergey Svishchev in private mail.
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Release Note for Icarus Verilog Snapshot 20070123
Handling of arrays has been rewritten to allow support for net
arrays. This caused ivl_target API changes, as well as elaboration and
vvp run time changes. There may be bits of the old method lingering in
the source code.
Improve support for constant power (**) expressions, and other
constant exppressions that are passed to functions/tasks.
Improve elaboration of for-loop increment expressions. There were some
bugs there that are not fixed.
Fix argument width calculations for shift operations.
Constant ector expressions can have real constants. Handle this at run
time where needed.
Fix some bad lookaside optimizations for assignments to l-value part
selects.
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last snapshot. A highly abbreviated list is:
libgeda:
- fixes to postscript output
- fixes to arc handling
- added some functions for embedding and deembedding symbols
- many changes to the internal data structure.
- fix a bug which could cause missing connectivity on a bus
- improvements to attribute handling
- fix a bunch of compiler warnings.
- various other bug fixes
gschem:
- improvements and bug fixes to the autonumber code
- improvements to the various file selection dialogs
- improvements to attribute handling
- improvements to the internal data structure
- various other bug fixes
gnetlist:
- fixes for guile-1.8
- update the gsch2pcb backend to allow running or never running m4 for pcb
footprints.
- changed "package" to "refdes" in the BOM/BOM2 backends
- added a drc2 regression test
- bugfix in the allegro backend
- other misc fixes
symbols:
- added 4 missing characters to complete the hungarian character set
- add greek mu
gsymcheck:
- man page improvements
gattrib:
- enhanced sorting functions
- various bug fixes
utils:
- add an option to gsch2pcb to let the user prevent m4 from ever being run
when looking for pcb footprints.
- let gsch2pcb look both for "name" and "name.fp" when looking for a footprint
called "name".
- use some configure options to set the default gsch2pcb footprint search paths
rather than hardcoding them.
- added a gnet_hier_verilog.sh script to do non-flattened verilog netlisting
- added options to gschlas to embed or de-embed all symbols in a schematic
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========================================================================
Release Notes for PCB snapshot 20070208
========================================================================
- Add polygon clipping code. This is a big change to how polygons are handled.
The new code now removes islands and correctly identifies open circuits caused
by a trace fully cutting through a polygon. In addition, the RS-274-X output
is now simpler and works with some board houses that use older non-conforming
sofware. Different styles for thermal reliefs are also now supported as part
of the polygon clipper code.
- Add support for plugins
- Many improvements to the autorouter.
- Various improvements to the trace optimizer.
- Add a fontmode for editing pcb fonts
- Add progress() hook to HID structure
- Fix a bug with non-functional windows on some window managers commonly
found on OS-X
- Add support for controlling pcb via dbus
- Fix various bugs which would cause a crash
- Add --scale for postscript scaling
- Intercept window manager delete events with the GTK gui
- Scan the .pcb file for a FileVersion value. This is not written out yet
but will be in future versions.
- Warn if non-manhattan lines are trying to become pads.
- Allow no-solder paste pads to support fiducials
- Report in mm or mils as selected by user
- Allow reordering of layers
- add some more QFN packages
- fix building with sun studio c compiler
- Made a pcb installation be relocatable.
- Convert the m4 libraries to newlib libraries as part of building a distfile.
The m4 libraries are still considered the sources and as such are still
distributed but this eliminates the need for m4 at runtime for footprints.
- Got rid of the pcb wrapper script around pcb-bin.
- Remove some old footprints of questionable naming, accuracy, or usefulness.
- Get the autosave/backup code working on all GUI's
- Fix some drill size rounding in the reports
- Changed the backup file name to be derived from the .pcb file name
- Added a command line option for DrawGrid
- Fix logic for adding new ratlines
- Fix gtk grid when board is flipped
- Add "find" and "rip-up" buttons to the netlist window
- Draw plated holes when exporting
- Fix some bugs when converting selection to element
- Fix build on cygwin
- Enhance the win32/build_pcb script used to generate a non-cygwin windows
installer.
- Make pcb work under non-cygwin windows
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SimPy 1.8 is a major release with new capabilities, improved documentation
and bug fixes. It is fully backwards compatible with previous versions.
From SimPy 1.8 on, the obsolete Python version 2.2 is no longer supported.
Some of the changes and improvements are:
* New compound yield statements, supporting time-out or event-based
reneging in 'get' and 'put' operations on Store and Level resources.
* yield get on a Store resource can now have a filter function which
selects which and how many items (e.g. "3 parcels weighing less than
3 pounds") should be retrieved.
* The Manual has been thoroughly edited, restructured and rewritten
with a view to greater clarity and readability. It is provided in both
HTML and PDF format.
* The Cheatsheet has been completely rewritten in a tabular format and
reduced to just a few pages. The goal was to turn it into a concise
desktop reference of SimPy commands. The Cheatsheet is provided in both
XLS (MS Excel spreadsheet) and PDF format.
SimPy 1.7.1 is a minor (maintenance) release which fixes a few bugs
in 1.7. The SimPy 1.7.1 API is identical to that of version 1.7.
SimPy 1.7 is fully compatible with version 1.6.1. This major release brings
significant new capabilities for the SimPy modeller and thus a broader
field of applicability to SimPy. It is now very easy to implement models
for scenarios involving:
* producer/consumer relationships between processes,
* multi-process cooperations,
* multi-resource requests, and
* consumable resources.
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Error: An integer constant expression is required within the array subscript operator.
VS: ----------------------------------------------------------------------
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files. This allows setting INSTALLATION_PREFIX for the package.
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AC_PROG_CXX to find a c++ compiler. This fixes building with sunpro.
The result seems to run ok. Patches submitted upstream.
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environments.
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depends bump.
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INSTALLATION_DIRS, as well as all occurrences of ${PREFIX}/man with
${PREFIX}/${PKGMANDIR}.
Fixes PR 35265, although I did not use the patch provided therein.
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PKGREVISION++
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