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LC is simulation tool for the analysis of the electromagnetic
properties of electrical interconnects. The full three-dimensional
circuit is modeled, so all interactions are automatically included in
the solution. The model can be excited by numerous types of waveforms,
and the transient response measured using common values such as
voltage and current. Circuit parameters such as inductance,
capacitance, and impedance can be derived from the transient response,
and frequency-domain results such as S-parameters can also be
calculated. Far field radiation patterns can be obtained.
LC is primarily an electromagnetic simulation and uses the
Finite-Difference Time-Domain (FD-TD) technique. FD-TD is a full wave
explicit solution of Maxwell's equations in three dimensions. In FD-TD,
the rectangular volume enclosing the model is discretized into a large
number of small cells, which may be uniformly-sized, or may vary in size
within the simulation space. The dielectric, permeable, lossy, and
conducting material properties of each cell are incorporated into the
field updates, which are performed iteratively in small time steps.
An interface between the electromagnetic simulation and the circuit
simulation program SPICE is available within LC. This allows the user
to add arbitrary SPICE circuits, such as drivers and loads, into the
interconnect model. The interconnect performance is calculated using
FD-TD while the lumped-element circuits are evaluated by SPICE.
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version 6.9
Update for wxWidgets 2.6.2
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Patch provided by Sergey Svishchev in private mail.
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From Sergey Svishchev in private mail.
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Release Note for Icarus Verilog Snapshot 20070123
Handling of arrays has been rewritten to allow support for net
arrays. This caused ivl_target API changes, as well as elaboration and
vvp run time changes. There may be bits of the old method lingering in
the source code.
Improve support for constant power (**) expressions, and other
constant exppressions that are passed to functions/tasks.
Improve elaboration of for-loop increment expressions. There were some
bugs there that are not fixed.
Fix argument width calculations for shift operations.
Constant ector expressions can have real constants. Handle this at run
time where needed.
Fix some bad lookaside optimizations for assignments to l-value part
selects.
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last snapshot. A highly abbreviated list is:
libgeda:
- fixes to postscript output
- fixes to arc handling
- added some functions for embedding and deembedding symbols
- many changes to the internal data structure.
- fix a bug which could cause missing connectivity on a bus
- improvements to attribute handling
- fix a bunch of compiler warnings.
- various other bug fixes
gschem:
- improvements and bug fixes to the autonumber code
- improvements to the various file selection dialogs
- improvements to attribute handling
- improvements to the internal data structure
- various other bug fixes
gnetlist:
- fixes for guile-1.8
- update the gsch2pcb backend to allow running or never running m4 for pcb
footprints.
- changed "package" to "refdes" in the BOM/BOM2 backends
- added a drc2 regression test
- bugfix in the allegro backend
- other misc fixes
symbols:
- added 4 missing characters to complete the hungarian character set
- add greek mu
gsymcheck:
- man page improvements
gattrib:
- enhanced sorting functions
- various bug fixes
utils:
- add an option to gsch2pcb to let the user prevent m4 from ever being run
when looking for pcb footprints.
- let gsch2pcb look both for "name" and "name.fp" when looking for a footprint
called "name".
- use some configure options to set the default gsch2pcb footprint search paths
rather than hardcoding them.
- added a gnet_hier_verilog.sh script to do non-flattened verilog netlisting
- added options to gschlas to embed or de-embed all symbols in a schematic
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========================================================================
Release Notes for PCB snapshot 20070208
========================================================================
- Add polygon clipping code. This is a big change to how polygons are handled.
The new code now removes islands and correctly identifies open circuits caused
by a trace fully cutting through a polygon. In addition, the RS-274-X output
is now simpler and works with some board houses that use older non-conforming
sofware. Different styles for thermal reliefs are also now supported as part
of the polygon clipper code.
- Add support for plugins
- Many improvements to the autorouter.
- Various improvements to the trace optimizer.
- Add a fontmode for editing pcb fonts
- Add progress() hook to HID structure
- Fix a bug with non-functional windows on some window managers commonly
found on OS-X
- Add support for controlling pcb via dbus
- Fix various bugs which would cause a crash
- Add --scale for postscript scaling
- Intercept window manager delete events with the GTK gui
- Scan the .pcb file for a FileVersion value. This is not written out yet
but will be in future versions.
- Warn if non-manhattan lines are trying to become pads.
- Allow no-solder paste pads to support fiducials
- Report in mm or mils as selected by user
- Allow reordering of layers
- add some more QFN packages
- fix building with sun studio c compiler
- Made a pcb installation be relocatable.
- Convert the m4 libraries to newlib libraries as part of building a distfile.
The m4 libraries are still considered the sources and as such are still
distributed but this eliminates the need for m4 at runtime for footprints.
- Got rid of the pcb wrapper script around pcb-bin.
- Remove some old footprints of questionable naming, accuracy, or usefulness.
- Get the autosave/backup code working on all GUI's
- Fix some drill size rounding in the reports
- Changed the backup file name to be derived from the .pcb file name
- Added a command line option for DrawGrid
- Fix logic for adding new ratlines
- Fix gtk grid when board is flipped
- Add "find" and "rip-up" buttons to the netlist window
- Draw plated holes when exporting
- Fix some bugs when converting selection to element
- Fix build on cygwin
- Enhance the win32/build_pcb script used to generate a non-cygwin windows
installer.
- Make pcb work under non-cygwin windows
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SimPy 1.8 is a major release with new capabilities, improved documentation
and bug fixes. It is fully backwards compatible with previous versions.
From SimPy 1.8 on, the obsolete Python version 2.2 is no longer supported.
Some of the changes and improvements are:
* New compound yield statements, supporting time-out or event-based
reneging in 'get' and 'put' operations on Store and Level resources.
* yield get on a Store resource can now have a filter function which
selects which and how many items (e.g. "3 parcels weighing less than
3 pounds") should be retrieved.
* The Manual has been thoroughly edited, restructured and rewritten
with a view to greater clarity and readability. It is provided in both
HTML and PDF format.
* The Cheatsheet has been completely rewritten in a tabular format and
reduced to just a few pages. The goal was to turn it into a concise
desktop reference of SimPy commands. The Cheatsheet is provided in both
XLS (MS Excel spreadsheet) and PDF format.
SimPy 1.7.1 is a minor (maintenance) release which fixes a few bugs
in 1.7. The SimPy 1.7.1 API is identical to that of version 1.7.
SimPy 1.7 is fully compatible with version 1.6.1. This major release brings
significant new capabilities for the SimPy modeller and thus a broader
field of applicability to SimPy. It is now very easy to implement models
for scenarios involving:
* producer/consumer relationships between processes,
* multi-process cooperations,
* multi-resource requests, and
* consumable resources.
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Error: An integer constant expression is required within the array subscript operator.
VS: ----------------------------------------------------------------------
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files. This allows setting INSTALLATION_PREFIX for the package.
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AC_PROG_CXX to find a c++ compiler. This fixes building with sunpro.
The result seems to run ok. Patches submitted upstream.
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environments.
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depends bump.
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INSTALLATION_DIRS, as well as all occurrences of ${PREFIX}/man with
${PREFIX}/${PKGMANDIR}.
Fixes PR 35265, although I did not use the patch provided therein.
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PKGREVISION++
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compiler. Patch is already in the upstream sources.
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Patch is already in upstream sources.
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Builds on solaris with sun studio compilers now. Patch already in the
upstream sources.
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packages with the modular Xorg equivalent. Those are falling back
to the old location by default, so this commmit doesn't change
dependencies.
graphics/xpm ==> x11/libXpm
fonts/Xft2 ==> x11/libXft
x11/Xfixes ==> x11/libXfixes
x11/xcursor ==> x11/libXcursor
x11/Xrender ==> x11/libXrender
x11/Xrandr ==> libXrandr
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There have been many updates and minor versions between the last packaged
version and this one. These updates have included many bug fixes including
several bugs which would cause a crash, bugs in the generated netlists,
and others.
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Release notes for the gEDA/gaf 20061020 snapshot
Changes
_________________________________________________________________
libgeda/gschem
libgeda and gschem no longer use libgdgeda (which was a gEDA specific
hack to the libgd library). gEDA/gaf now wants to use the original
GD library. (Wojciech Kazubski and Carlos Nieves Onega with
cleanup by others)
*
* gEDA/gaf now compiles out of the box on cygwin. (Cesar Strauss)
* Fixed bug #1553544: "New pages inadvertently created when adding
nets in gschem" (Peter Clifton)
* New component selection dialog box for gschem. This one is so much
better than the original one. Please test it out and submit
comments to the mailing lists. (Patrick Bernaud)
* The preview window is inside the file selectors again. The preview
window has been refactored and improved. (Patrick Bernaud)
* gschem now places a title block (or any component the user wants)
when a new page/window is created. This solves the common complain
that the initial zoom is way to far out. (Carlos Nieves Onega)
* Improvements to the new print dialog box: Make print settings
sticky for session. (Peter Brett)
* Fixed bug #1527465: Do a zoom extents for all pages when the main
window is maximized. (Carlos Nieves Onega and others)
* Fixed bug #1565433: Added the border in the gdk-pixbuf's image
output. (Carlos Nieves Onega)
* New dialog for user confirmation before closing a page or a
window. This is also a great improvement over the previous exit
confirm dialog box. (Patrick Bernaud)
* Various language translations updated.
* libgeda's shared library version is now 27:0:0.
* Many more bug fixes and code cleanups. (various people)
gnetlist
* Fixed PCB cursor related issues (Peter Clifton and Stuart
Brorson).
* Minor cleanup of gnet-PCB backend. (Thien-Thi Nguyen)
gattrib
* Made gattrib throw up GUI window warning user of no components or
attributes. (Stuart Brorson)
* File browsers in gattrib are now the same ones that gschem uses.
(Patrick Bernaud)
* The usual bug fixes and code cleanup. (various)
docs
* Updated the wiki snapshot to the latest web wiki version.
symbols
* linear/lm311-1.sym: Removed the GND false connection of the
symbol. (Ramakrishnan Muthukrishnan, John Luciani, and Carlos
Nieves Onega).
* Lots of off grid symbols cleaned up. (Werner Hoch)
gsymcheck
* Adds newline that is missing from the "Found Pintype=..." message
in s_check_pintype() in s_check.c. (Jeff Mallatt and Carlos Nieves
Onega)
* gsymcheck now counts the number of distinct pinnumbers specified
in all slotdef= attributes. Uses that number, plus the number of
net= pins, to compare with the "footprint size" when checking for
that warning. (Jeff Mallatt and Carlos Nieves Onega).
utils
* Applied patches for the cygwin port. Lots of various improvements
to make gschemdoc more Windows friendly (at least under cygwin).
(Cesar Strauss, Peter Brett, and Carlos Nieves Onega)
examples
* No significant changes
For more a detailed changes, please look in the appropriate ChangeLogs
in the source tarballs.
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* 09/04/2006
Development release covered-20060904 made. This is primarily an enhanced language support release
containing support for the Verilog-2001 'generate' block and support for some SystemVerilog constructs.
All bug fixes from the stable release branch have also been included in this release as well. Some
updates to the GUI (to match changes made on the score command side). The following is a list of
changes made from the last development release
- Complete parsing/simulation support for generate blocks include generate for, if/else and
case constructs.
- Fixed bug in hierarchically referencing items within an array of instances.
- Added -g option to score command to allow the user to specify on either a global or modular
level which Verilog generation to consider for that design. This allows a block of logic written
with Verilog-1995 in mind to use names that would be keywords in Verilog-2001 or SystemVerilog,
as an example.
- Removed "manstyle" type documentation in user's guide as this tool is no longer used for this
project. This change should be transparent to the user, however.
- Fixed scoping/hierarchical referencing rules to match the Verilog LRM properly.
- Added parsing/handling support for SystemVerilog always_comb, always_ff and always_latch blocks.
- Added parsing support for 'unique' and 'priority' SystemVerilog keywords before if and case
statements (Covered doesn't need to do anything with them, however).
- Added parsing/handling support for 'do .. while' SystemVerilog loops.
- Added parsing/handling support for new SystemVerilog data types, including: byte, bit, logic,
char, shorting, int and longint.
- Added -rI option to the score command which allows the user to completely bypass the race
condition checking phase of the score command.
- Added -B global option which obfuscates all identifying names from Covered's output (for use
in providing debugging information to the developer's of Covered).
- Added parsing/handling support for operate-and-assign SystemVerilog operators, including:
+=, -=, *=, /=, %=, &=, |=, ^=, <<=, >>=, <<<=, >>>=, ++ and --. These can be used wherever
their counterparts can be used (including generate for loops).
- Added proper handling of Verilog-1995 delayed blocking assignments (i.e., "a = #5 b;" or
"a = @(posedge clk) c;"). Previously, the delay was being incorrectly ignored which could
have lead to infinite looping of always/forever blocks or could calculate incorrect coverage
information.
- Added parsing support for SystemVerilog .name and .* port lists.
- Added partial parsing/handling support for SystemVerilog 'typedef' usage. This should work for
enumerations but not other data types at this point.
- Added parsing/handling support for SystemVerilog 'enum' constructs. These should be fully
supported with the exception of their built-in '.first', '.last', '.next', '.prev', '.num' and
'.name' methods.
- Added full support of handling Verilog-1995 repeated delay blocking assignments (i.e.,
"a = repeat(5) @(posedge clk) b;". These were previously being treated as normal blocking
assignments.
- Added keyword highlighting support in GUI for Verilog-2001 and SystemVerilog keywords depending
on the -g value specified for a particular module.
- Added parsing support for SystemVerilog assertion, property and sequence blocks. These constructs
are ignored by the parser but should not cause a parsing error now.
- Added parsing support for SystemVerilog multi-dimensional arrays. These are ignored by the
parser but should not cause an error.
- Added full support for the SystemVerilog $root global space -- though limited testing has
been performed with this at this point.
- Added -s option to the report command to suppress the output for modules/instances that contain
no coverage information.
- Updated all user documentation to match changes made for this development release.
- Lots of new diagnostics added to regression suite to verify the majority of these changes.
There you have it. A lot of enhancements made for language support for Verilog-1995, Verilog-2001
and SystemVerilog. Some of the additions for SystemVerilog, especially typedefs and $root global
space, have not been fully verified to work and may still be a bit buggy, but everything else should
be expected to work as advertised. Please submit any bugs that you find. The next development
release should contain support for some more language enhancements, including full support for
typedef and enumeration usage, support for memories, multi-dimensional arrays, structs and unions.
I will also be looking at adding support for bitwise coverage information (for vectored calculations).
As always, have fun!
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* 08/30/2006
Stable release covered-0.4.7 made. This release is mostly a bug fix release with two feature
additions. The new feature is the global -B option was performs name obfuscation on all identifying,
design-sensitive names from all output (with the exception of CDD file output). This option is
mostly useful as a way to share debugging information with the maintainer(s) of Covered without giving
away sensitive information. Additionally, the -rI score option was added to allow user's to completely
skip the race condition checking phase. This allows users to force Covered to consider all code for
coverage (if race condition checking is performed, all code considered to be potential race conditions
are automatically excluded from coverage consideration). User documentation has been updated for these
changes. The following lists the changes in this release.
- Fixed bug 1535412. Implicit event expressions (i.e., "always @*") now traverse named begin/end
blocks correctly to search for RHS variables.
- Fixed bugs related to segmentation faults and memory leak issues
- Fixed hierarchical reference search to match Verilog-1995 LRM
- Fixed bug 1538922. If -vcd or -lxt option was specified twice, an incorrect error message was
displayed to the user.
- Added -rI option to allow user's to bypass the race condition checking step in the score command.
- Fixed bug 1538920. Handling of any-edge triggered events (i.e., "@(b)") was incorrectly handled
by Covered. Additionally, fixed the event trigger operator (->) to work correctly with the new
changes.
- Fixed bug 1541944. Command options that require a value are now checked to make sure that a value
exists, and an appropriate error message is output if this is not achieved.
- Fixed bug 1542454. Command options that must only be allowed once on a command-line are now
checked and handled appropriately (caused a segmentation fault previously).
- Fixed bug 1544322. When an AND- or OR-type expression has either a left or right expression evaluate
to 0 or 1, respectively, Covered now outputs correct coverage information when the opposite expression
evaluates to an X or Z value, simultaneously.
- Fixed bug 1544325. Multi-variable expressions are now always output as such in report files.
- Fixed bug 1544169. Avoiding consideration of named begin/end block keywords in line coverage.
- Fixed bug 1546059. Covered now properly handles the removal of statement blocks that cannot be
considered for coverage which also contain parameters from another functional unit block.
- Fixed bug with connection of statements in a statement block.
- Updated documentation to match new features added in this release.
* 07/22/2006
Stable release covered-0.4.6 made. This release contains several bug fixes that are listed below.
- Fixed segmentation fault bug which occurs when a multi-bit select on the LHS contains any
expression besides static values.
- Fixed several memory leaks found with valgrind
- Fixed bug 1520159 - arrays of instances incorrectly always started at index 0.
- Fixed bug 1521598 having to do with reduction unary invert and logical not operators not
calculating correctly.
- Fixed bug in db_read when a functional unit is being merged to point to the used module.
- Fixed assertion in link.c such that no segmentation fault occurs if a string is not found
in a str_link list for deletion.
- Fixed bug pertaining to embedded concatenations within function/task parameter lists.
- Fixed bug pertaining to empty named begin-end blocks.
- Fixed bug in the db_read function that would cause Covered to flag an internal assertion
error if an error occurred while reading the CDD file and the global -D option was specified.
- Fixed upwards name referencing bug (1524705).
- Enhanced regression suite to verify that all of these bugs are properly fixed.
* 07/08/2006
Stable release covered-0.4.5 made. This release contains a bug fix to properly handle cases
where two or more signals are declared with a parameter in their range field (i.e., reg [FOO:0] a, b;)
This caused Covered to segfault due to attempting to free the same address twice. Bug 1518932.
Also contains a bug fix to properly remove statement blocks that contain case, casex or casez
expressions and unbindable expressions.
* 5/28/2006
Stable release covered-0.4.4 made. This release contains a bug fix to proper handle hierarchical
referencing of parameter values. This feature was technically not supported in the past but caused
an internal assertion error when this was performed. The feature is now fully supported.
* 4/21/2006
Stable release covered-0.4.3 made. This release contains a bug fix to the statement connection function that
caused segmentation faults during the score command. Also added support for big endian wires/regs. This
information was being ignored by the parser and, consequently, was not being handled correctly by Covered's
internal simulator, leading to incorrect coverage information. The lack of this support was also causing
an internal error in the memory allocation routine when scoring the dumpfile.
* 4/17/2006
Stable release covered-0.4.2 made. This release contains a bug fix that caused an assertion error in the
binding.c source file to occur. The reason for this assertion was a syntax error in the parser that caused
problems when more than one task call was made in a statement block. Also added support for multi-line
definitions (i.e., a '\' character used at the end of a definition line). This was missing but was not meant
to be missing.
* 4/4/2006
Stable release covered-0.4.1 made. This release contains one bug fix that causes an assertion error when
compiling designs that use a concatenation operation on the left-hand-side of assignment statements. If
you are experiencing this problem with the 0.4 release, it is recommended that you use this new release
instead.
* 3/29/2006
Stable release covered-0.4 made. In addition to all of the features, optimizations and bug fixes
that have gone into the development releases from the 0.3 stable release, the following features, updates
and bug fixes have been added.
- Fixed bug with a statement connection issue that causes lines of code to be not considered for
coverage that should have been.
- Fixed bug in report command where combinational expressions were not being output to match the original
Verilog code.
- Added CDD file viewer window to GUI to allow the user to see which CDD files are currently loaded/merged.
- Fixed bug in combinational logic verbose viewer which caused the window to resize dependent upon
the location of the cursor (this was an annoyance)
- Changed the output of simple combinational logic to change to unary combinational logic output if either
the left or the right expression was a constant value (eliminates unachievable combinational logic cases
from being output leading to more accurate coverage results).
- Removed combinational expressions that contain only constant values from being considered for coverage.
- Updated simple combinational logic output in reports to be as concise as possible for AND and OR type
expressions.
- Removed duplication of information in CDD files for race conditions.
- Fixed bug in GUI dealing with showing race conditions
- Fixing bug in GUI pertaining to the next/previous buttons in the combinational logic detail viewer. Previously,
clicking on one of these buttons would only advance you to the next uncovered line. Now it will advance
you to the next uncovered statement.
- Updated development, user and GUI documentation to reflect the above changes and to bring them up-to-date
with the rest of the tool.
Please see the ChangeLog file for all changes made from the 0.3 stable release to the 0.4 stable release.
Lots of enhancements, features, optimizations, bug fixes, performance improvements and documentation improvements
are contained in this stable release, making it very worth while for any Covered users to get their hands on
it.
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wait(). Patch (or equivalent) will be applied upstream.
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* Release Notes for Icarus Verilog Snapshot 20061009
The Big news is support for delay path timing is specify blocks. This
includes delay paths and specparams. Back annotation of specify path
timings are not yet implemented.
The "-g" flag has been made a bit more general so that individual
compiler features can be turned on/off. This for example allows for
turning off specify block support and Icarus Verilog extensions, as
well as select language generation.
A variety of bug fixes have been included.
- Missing symbols on Windows fixed.
- mingw build instructions reworked.
- Fix internal handling of -D__ICARUS__ define
- Fix crash of driver when -M flag is used.
- Fix configure detection of host in some subdirectories.
- Handle non-constant delays of index non-blocking assignments.
- $scanf support for real values.
- Fix scheduling of RWsync vs. ROSync callbacks.
- Fix vpi_put_userdata return value.
The iverilog-vpi command now allows .cpp files to stand for C++
source.
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** Release Notes for Icarus Verilog 0.8.3
This is a new release of the stable 0.8 branch. The changes from 0.8.2
are intended to be evolutionary, rather then revolutionary, to enhance
the stability of the branch.
Various simulator bugs have been fixed, including (but not limited to):
- Detect overrun of timescale vs. precision
- Handle more operators in constant expressions
- Various ivl crashes and panics fixed.
- Some performance bottlenecks have been fixed.
- Various tool compilation problems have been fixed.
Also, the internal synthesizer (for synthesis targets) has been
considerably improved. NOTE that the code generators have not been
improved to take advantage of all the changes here, so there is work
yet to be done.
The mingw build process for compiling in Windows has been reworked. It
is now possible (indeed preferable) to compile fully native Icarus
Verilog binaries on Windows with no Cygwin tools at all.
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