From 89c6f160702c2a13560d002e3369a4c3e90f9459 Mon Sep 17 00:00:00 2001 From: dmcmahill Date: Thu, 22 Jun 2000 03:15:31 +0000 Subject: update to verilog-0.3 Changes, from the authors release statement, are: This release is a significant improvement over previous releases of Icarus Verilog, including better language coverage, improved synthesis, and increased performance. This release adds to the 0.2 release support for Verilog-2000 style parameters and parameter overrides, defparam, and localparam, including proper handling of scoping rules. Also, strength modeling is added, with support for strengths attached to gates and continuous assignments. Combinational user defined primitives have been added to complement synchronous primitives that were already supported. Support for primitives should now be fairly complete. Force/release/assign/deassign syntax now works properly, allowing for more sophisticated test bench design and debugging. Bug fixes have been numerous and varied. This release of Icarus Verilog is considerably more robust then previous versions, thanks to diligent testing and bug reporting by users all over the world. --- cad/verilog/Makefile | 19 ++++++++++--------- cad/verilog/files/md5 | 4 ++-- cad/verilog/files/patch-sum | 6 +++--- cad/verilog/patches/patch-ab | 11 +++++++++++ cad/verilog/patches/patch-ad | 8 ++++---- cad/verilog/patches/patch-ae | 13 ------------- cad/verilog/pkg/PLIST | 15 ++++++++------- 7 files changed, 38 insertions(+), 38 deletions(-) create mode 100644 cad/verilog/patches/patch-ab delete mode 100644 cad/verilog/patches/patch-ae diff --git a/cad/verilog/Makefile b/cad/verilog/Makefile index c0f729add4d..367b269df49 100644 --- a/cad/verilog/Makefile +++ b/cad/verilog/Makefile @@ -1,18 +1,19 @@ -# $NetBSD: Makefile,v 1.3 2000/03/07 16:05:13 dmcmahill Exp $ +# $NetBSD: Makefile,v 1.4 2000/06/22 03:15:31 dmcmahill Exp $ # -DISTNAME= verilog-0.2 -CATEGORIES= cad -MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v0.2/ +DISTNAME= verilog-0.3 +CATEGORIES= cad +MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v0.3/ -MAINTAINER= dmcmahill@netbsd.org -HOMEPAGE= http://icarus.com/eda/verilog/index.html +MAINTAINER= dmcmahill@netbsd.org +HOMEPAGE= http://icarus.com/eda/verilog/index.html -BUILD_DEPENDS+= bison:../../devel/bison +BUILD_DEPENDS+= bison:../../devel/bison +BUILD_DEPENDS+= gperf:../../devel/gperf -CONFLICTS+= verilog-current +CONFLICTS+= verilog-current GNU_CONFIGURE= yes -USE_GMAKE= yes +USE_GMAKE= yes .include "../../mk/bsd.pkg.mk" diff --git a/cad/verilog/files/md5 b/cad/verilog/files/md5 index 97491292900..35a7603a908 100644 --- a/cad/verilog/files/md5 +++ b/cad/verilog/files/md5 @@ -1,3 +1,3 @@ -$NetBSD: md5,v 1.3 2000/03/07 16:05:14 dmcmahill Exp $ +$NetBSD: md5,v 1.4 2000/06/22 03:15:32 dmcmahill Exp $ -MD5 (verilog-0.2.tar.gz) = 41f0a1cbc46b8b34df9f785f3c5c9ebd +MD5 (verilog-0.3.tar.gz) = eebe52780df6adcc436942bc2de2969c diff --git a/cad/verilog/files/patch-sum b/cad/verilog/files/patch-sum index 7914e83dd87..d7e9f131e33 100644 --- a/cad/verilog/files/patch-sum +++ b/cad/verilog/files/patch-sum @@ -1,4 +1,4 @@ -$NetBSD: patch-sum,v 1.3 2000/03/07 18:24:48 dmcmahill Exp $ +$NetBSD: patch-sum,v 1.4 2000/06/22 03:15:32 dmcmahill Exp $ -MD5 (patch-ad) = 35aae681e397bc9d5be0f6765a8adc96 -MD5 (patch-ae) = 44921f529c17458cd3ba34d35dc0da77 +MD5 (patch-ab) = 8e1ec1875b9f1c8a969205c81598be94 +MD5 (patch-ad) = d875516e4fc53270d66101a60bc1e8e5 diff --git a/cad/verilog/patches/patch-ab b/cad/verilog/patches/patch-ab new file mode 100644 index 00000000000..8c67ee3dc79 --- /dev/null +++ b/cad/verilog/patches/patch-ab @@ -0,0 +1,11 @@ +$NetBSD: patch-ab,v 1.3 2000/06/22 03:15:32 dmcmahill Exp $ + +--- vpi/Makefile.in.orig Wed May 3 23:37:59 2000 ++++ vpi/Makefile.in Sun Jun 11 18:59:57 2000 +@@ -42,5 +42,5 @@ + INSTALL_DATA = @INSTALL_DATA@ + +-CPPFLAGS = @CPPFLAGS@ @DEFS@ -fpic ++CPPFLAGS = @CPPFLAGS@ @DEFS@ -fPIC + CXXFLAGS = @CXXFLAGS@ + LDFLAGS = @LDFLAGS@ diff --git a/cad/verilog/patches/patch-ad b/cad/verilog/patches/patch-ad index c417b9acdf4..ce256dfff6d 100644 --- a/cad/verilog/patches/patch-ad +++ b/cad/verilog/patches/patch-ad @@ -1,11 +1,11 @@ -$NetBSD: patch-ad,v 1.3 2000/03/07 18:24:49 dmcmahill Exp $ +$NetBSD: patch-ad,v 1.4 2000/06/22 03:15:32 dmcmahill Exp $ don't use -O2 on parse.cc because of compiler bugs on sparc and pmax (maybe others). ---- Makefile.in.orig Sat Feb 5 01:40:35 2000 -+++ Makefile.in Tue Mar 7 12:38:25 2000 -@@ -111,4 +111,6 @@ +--- Makefile.in.orig Fri Apr 28 12:50:53 2000 ++++ Makefile.in Sat Apr 29 08:39:00 2000 +@@ -115,4 +115,6 @@ parse.o dep/parse.d: parse.cc + $(CXX) -MD -c -I. $(CPPFLAGS) $< diff --git a/cad/verilog/patches/patch-ae b/cad/verilog/patches/patch-ae deleted file mode 100644 index aeb7ae6f39a..00000000000 --- a/cad/verilog/patches/patch-ae +++ /dev/null @@ -1,13 +0,0 @@ -$NetBSD: patch-ae,v 1.2 2000/02/14 22:55:33 dmcmahill Exp $ - -use the correct flag for our compiler. - ---- verilog.sh.orig Sat Feb 5 01:40:35 2000 -+++ verilog.sh Sun Feb 13 11:15:00 2000 -@@ -117,5 +117,5 @@ - "xnf") mv ${tmpCCFile} ${outputFile} ;; - -- "vvm") ${execCpp} -rdynamic -I${includedir} -L${libdir} ${tmpCCFile} -o ${outputFile} -lvvm @dllib@ ; -+ "vvm") ${execCpp} -Wl,--export-dynamic -I${includedir} -L${libdir} ${tmpCCFile} -o ${outputFile} -lvvm @dllib@ ; - if test $? -ne 0 ; then - echo "C++ compilation failed. Terminating compilation." diff --git a/cad/verilog/pkg/PLIST b/cad/verilog/pkg/PLIST index b4afbadd981..a0e65cb9165 100644 --- a/cad/verilog/pkg/PLIST +++ b/cad/verilog/pkg/PLIST @@ -1,16 +1,17 @@ -@comment $NetBSD: PLIST,v 1.1.1.1 2000/01/26 15:28:40 dmcmahill Exp $ -bin/verilog -bin/gverilog +@comment $NetBSD: PLIST,v 1.2 2000/06/22 03:15:33 dmcmahill Exp $ +bin/iverilog +include/vpi_priv.h include/vpi_user.h include/vvm.h -include/vpi_priv.h +include/vvm_calltf.h include/vvm_func.h include/vvm_gates.h +include/vvm_nexus.h +include/vvm_signal.h include/vvm_thread.h -include/vvm_calltf.h lib/ivl/ivl -lib/ivl/system.vpi lib/ivl/ivlpp +lib/ivl/system.vpi lib/libvvm.a -man/man1/verilog.1 +man/man1/iverilog.1 @dirrm lib/ivl -- cgit v1.2.3