From c62f699f8b41ae4a7534ea14d00fcfc2eeb8f76c Mon Sep 17 00:00:00 2001
From: drochner <drochner@pkgsrc.org>
Date: Fri, 10 Feb 2006 17:05:03 +0000
Subject: import MyHDL-iverilog-0.5, an Icarus Verilog vpi module to support
 cosimulation from py-MyHDL

---
 cad/MyHDL-iverilog/DESCR    |  7 +++++++
 cad/MyHDL-iverilog/Makefile | 20 ++++++++++++++++++++
 cad/MyHDL-iverilog/PLIST    |  2 ++
 cad/MyHDL-iverilog/distinfo |  5 +++++
 4 files changed, 34 insertions(+)
 create mode 100644 cad/MyHDL-iverilog/DESCR
 create mode 100644 cad/MyHDL-iverilog/Makefile
 create mode 100644 cad/MyHDL-iverilog/PLIST
 create mode 100644 cad/MyHDL-iverilog/distinfo

diff --git a/cad/MyHDL-iverilog/DESCR b/cad/MyHDL-iverilog/DESCR
new file mode 100644
index 00000000000..fd819237dc9
--- /dev/null
+++ b/cad/MyHDL-iverilog/DESCR
@@ -0,0 +1,7 @@
+MyHDL is a Python package for using Python as a hardware
+description language. Popular hardware description languages, like
+Verilog and VHDL, are compiled languages. MyHDL with Python
+can be viewed as a "scripting language" counterpart of such
+languages. However, Python is more accurately described as a very
+high level language (VHLL). MyHDL users have access to the
+amazing power and elegance of Python for their modeling work.
diff --git a/cad/MyHDL-iverilog/Makefile b/cad/MyHDL-iverilog/Makefile
new file mode 100644
index 00000000000..4691dc1feee
--- /dev/null
+++ b/cad/MyHDL-iverilog/Makefile
@@ -0,0 +1,20 @@
+# $NetBSD: Makefile,v 1.1.1.1 2006/02/10 17:05:03 drochner Exp $
+#
+
+DISTNAME=	myhdl-0.5
+PKGNAME=	MyHDL-iverilog-0.5
+CATEGORIES=	cad python
+MASTER_SITES=	${MASTER_SITE_SOURCEFORGE:=myhdl/}
+
+MAINTAINER=	tech-pkg@NetBSD.org
+HOMEPAGE=	http://jandecaluwe.com/Tools/MyHDL/Overview.html
+COMMENT=	Icarus Verilog cosimulation support for py-MyHDL
+
+BUILD_DIRS+=	cosimulation/icarus
+
+do-install:
+	${INSTALL_DATA} ${WRKSRC}/cosimulation/icarus/myhdl.vpi \
+		${PREFIX}/lib/ivl
+
+.include "../../cad/verilog/buildlink3.mk"
+.include "../../mk/bsd.pkg.mk"
diff --git a/cad/MyHDL-iverilog/PLIST b/cad/MyHDL-iverilog/PLIST
new file mode 100644
index 00000000000..f18708e6adb
--- /dev/null
+++ b/cad/MyHDL-iverilog/PLIST
@@ -0,0 +1,2 @@
+@comment $NetBSD: PLIST,v 1.1.1.1 2006/02/10 17:05:03 drochner Exp $
+lib/ivl/myhdl.vpi
diff --git a/cad/MyHDL-iverilog/distinfo b/cad/MyHDL-iverilog/distinfo
new file mode 100644
index 00000000000..5e25e7dc1e5
--- /dev/null
+++ b/cad/MyHDL-iverilog/distinfo
@@ -0,0 +1,5 @@
+$NetBSD: distinfo,v 1.1.1.1 2006/02/10 17:05:03 drochner Exp $
+
+SHA1 (myhdl-0.5.tar.gz) = c97517d7b70d6e4a56f6a2576baa685d53c394d3
+RMD160 (myhdl-0.5.tar.gz) = 2cbc89c5c2bd61a636b64bf5654471900f940ffc
+Size (myhdl-0.5.tar.gz) = 759071 bytes
-- 
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