From cc2302da662e4765c55251880ec0ce332e758a2c Mon Sep 17 00:00:00 2001 From: dmcmahill Date: Tue, 19 Dec 2000 18:53:51 +0000 Subject: update verilog-current to 20001216. Changes since the last packaged snapshot are (from the authors announcements): Icarus Verilog snapshot 20001216 -------------------------------- This is the last snapshot before the holidays, so I hope it has your favorite present in it. A lot of PR#s have been dealt with, and for a brief moment I felt like I was getting ahead of the pending list:-) I've added support for non-integer times, at least in a few contexts. The `timescale directives should interact properly with the decimal point in delays, causing more accurate timing simulations. This should make vendor-supplied libraries work much better. I've added support for signed reg variables. Signed expressions should now generally do the right thing, but this feature needs much more testing, and many more tests in the test suite. However, I do know that signed comparisons should work properly. Bug reports for problems with signed arithmetic are encouraged. Many people have been having troubles with Cygwin compilation. The problem was with the latest version of binutils. Venkat came up with a solution that works with old and new binutils, so you can now compile with the very latest cygwin software. This should make things a lot easier for a lot of people. I've made initial steps toward an HP/UX port. The configure script should detect the right dl library to use, and the t-dll target should be able to load loadable targets. I am looking for a volunteer to take responsibility for the HP/UX port as I have no suitable machines. Said person should be able to compile Icarus Verilog, manage HP/UX specific portability issues, and be able to make precompiled packages when the stable release is out. I'm still looking for a similar volunteer for FreeBSD/{alpha,i386}. Some more progress was made on support for PALs. I'm close to choosing macrocell modes and configuring fuses. Won't be long now, folks. Icarus Verilog snapshot 20001129 -------------------------------- few more constant propagation improvements this time, most notably XOR an XNOR are now fairly complete. These are interesting as they are generated by comparison operators so show up pretty often. And it is common to compare numbers to constants. Thus, there are lots of oppor- tunities for gate elimination! Synthesis of unary ! now works. Unary ~| (reduction nor) should also be in good shape now, as should binary || (logical or). Synthesis of binary && is still a little shaky. Go ahead and file reports if you trip on it. Binary != was broken with XNF synthesis, so that is also fixed, along with a few cases of mangled XNF output. And there were also a few bugs related to the CE of inferred DFFs, that didn't get connected. A *big* problem with synthesis occurred with non-blocking assignment. Icarus Verilog simply failed to synthesize the r-value of the assignment and all kinds of bad things happened. I fixed this, it's better now. Whew! Lots of XNF synthesis bugs fixed! This is what happens when users take the time to submit good bug reports. There are also some bugs related to dead signal elimination that causes Icarus Verilog to crash in some synthesis cases. These have been fixed up so far as I know. I have slightly improved root module detection of iverilog. If there is only one module in a source file, it is pretty obvious that it is the root module, even if it has ports. This is a common case for XNF synthesis (especially when making small macros with Icarus Verilog) and should save some typing and confusion. --- cad/verilog-current/Makefile | 9 ++++++--- cad/verilog-current/files/md5 | 4 ++-- cad/verilog-current/files/patch-sum | 5 +++-- cad/verilog-current/patches/patch-aa | 11 +++++++++++ cad/verilog-current/patches/patch-ad | 10 +++++----- cad/verilog-current/pkg/PLIST | 4 +++- 6 files changed, 30 insertions(+), 13 deletions(-) create mode 100644 cad/verilog-current/patches/patch-aa diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile index 8d7863858ad..448d2f91ae7 100644 --- a/cad/verilog-current/Makefile +++ b/cad/verilog-current/Makefile @@ -1,8 +1,8 @@ -# $NetBSD: Makefile,v 1.9 2000/11/24 18:03:58 dmcmahill Exp $ +# $NetBSD: Makefile,v 1.10 2000/12/19 18:53:51 dmcmahill Exp $ # -DISTNAME= verilog-20001119 -PKGNAME= verilog-current-20001119 +DISTNAME= verilog-20001216 +PKGNAME= verilog-current-20001216 CATEGORIES= cad MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/ @@ -11,10 +11,13 @@ HOMEPAGE= http://icarus.com/eda/verilog/index.html BUILD_DEPENDS+= bison:../../devel/bison BUILD_DEPENDS+= gperf:../../devel/gperf +DEPENDS+= ipal-current>=20001210:../../cad/ipal-current CONFLICTS+= verilog GNU_CONFIGURE= yes USE_GMAKE= yes +CPPFLAGS+= -I${LOCALBASE}/include +CONFIGURE_ENV+= CPPFLAGS="${CPPFLAGS}" LDFLAGS+="${LDFLAGS}" .include "../../mk/bsd.pkg.mk" diff --git a/cad/verilog-current/files/md5 b/cad/verilog-current/files/md5 index 9a4733e41ce..98e966ae82a 100644 --- a/cad/verilog-current/files/md5 +++ b/cad/verilog-current/files/md5 @@ -1,3 +1,3 @@ -$NetBSD: md5,v 1.9 2000/11/24 18:07:57 dmcmahill Exp $ +$NetBSD: md5,v 1.10 2000/12/19 18:53:52 dmcmahill Exp $ -MD5 (verilog-20001119.tar.gz) = f03c11cadef641506df2ed251aae4f69 +MD5 (verilog-20001216.tar.gz) = 3d30b951cb9dbb85e8bf74191c7c9abf diff --git a/cad/verilog-current/files/patch-sum b/cad/verilog-current/files/patch-sum index cc143f64e05..1c81adb246d 100644 --- a/cad/verilog-current/files/patch-sum +++ b/cad/verilog-current/files/patch-sum @@ -1,3 +1,4 @@ -$NetBSD: patch-sum,v 1.9 2000/10/27 03:59:48 dmcmahill Exp $ +$NetBSD: patch-sum,v 1.10 2000/12/19 18:53:52 dmcmahill Exp $ -MD5 (patch-ad) = 9aa6b9a02f6737fa7b911738942cf7c9 +MD5 (patch-aa) = 2ab80a6d95583009b71b880dc4f264ac +MD5 (patch-ad) = a9da357e98b2a3ddf6572a0f51b2f5f7 diff --git a/cad/verilog-current/patches/patch-aa b/cad/verilog-current/patches/patch-aa new file mode 100644 index 00000000000..6d4a5667164 --- /dev/null +++ b/cad/verilog-current/patches/patch-aa @@ -0,0 +1,11 @@ +$NetBSD: patch-aa,v 1.5 2000/12/19 18:53:52 dmcmahill Exp $ + +--- tgt-pal/Makefile.in.orig Thu Dec 14 18:37:47 2000 ++++ tgt-pal/Makefile.in Sun Dec 17 07:52:23 2000 +@@ -63,5 +63,5 @@ + + pal.tgt: $O $(TGTDEPLIBS) +- $(CC) @shared@ -o $@ $O $(TGTLDFLAGS) -lipal ++ $(CC) @shared@ -o $@ $O $(TGTLDFLAGS) $(LDFLAGS) -lipal + + clean: diff --git a/cad/verilog-current/patches/patch-ad b/cad/verilog-current/patches/patch-ad index 2d6907075ea..072c3a150aa 100644 --- a/cad/verilog-current/patches/patch-ad +++ b/cad/verilog-current/patches/patch-ad @@ -1,13 +1,13 @@ -$NetBSD: patch-ad,v 1.7 2000/10/27 03:59:48 dmcmahill Exp $ +$NetBSD: patch-ad,v 1.8 2000/12/19 18:53:52 dmcmahill Exp $ work around a c++ -O2 bug which is present on at least sparc and pmax using egcs-1.1.1 ---- Makefile.in.orig Fri Jul 14 02:12:56 2000 -+++ Makefile.in Sat Aug 5 17:43:55 2000 -@@ -116,4 +116,7 @@ +--- Makefile.in.orig Fri Dec 8 20:17:38 2000 ++++ Makefile.in Sat Dec 16 19:07:25 2000 +@@ -137,4 +137,7 @@ - parse.o dep/parse.d: parse.cc + parse.o: parse.cc + @[ -d dep ] || mkdir dep + $(CXX) -MD -c -I. $(CPPFLAGS) $< + mv parse.d dep/parse.d diff --git a/cad/verilog-current/pkg/PLIST b/cad/verilog-current/pkg/PLIST index fdb37c8c1b9..62238ae2607 100644 --- a/cad/verilog-current/pkg/PLIST +++ b/cad/verilog-current/pkg/PLIST @@ -1,4 +1,4 @@ -@comment $NetBSD: PLIST,v 1.6 2000/11/24 18:07:58 dmcmahill Exp $ +@comment $NetBSD: PLIST,v 1.7 2000/12/19 18:53:52 dmcmahill Exp $ bin/iverilog include/ivl_target.h include/vpi_priv.h @@ -15,6 +15,8 @@ lib/libvvm.a lib/ivl/ivl lib/ivl/iverilog.conf lib/ivl/ivlpp +lib/ivl/null.tgt +lib/ivl/pal.tgt lib/ivl/system.vpi man/man1/iverilog.1 @dirrm lib/ivl -- cgit v1.2.3