From 9e3ed99fde9bea6f99c1e67364fa003b04aed52e Mon Sep 17 00:00:00 2001
From: drochner <drochner>
Date: Fri, 10 Feb 2006 16:06:46 +0000
Subject: update to 0.5 major changes: -supports Python decorator syntax for
 generators (needs 2.4) -intbv() doesn't have a default anymore -many
 improvements to Verilog conversion

---
 cad/py-MyHDL/Makefile | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

(limited to 'cad/py-MyHDL/Makefile')

diff --git a/cad/py-MyHDL/Makefile b/cad/py-MyHDL/Makefile
index 53590f6a464..56398018e7d 100644
--- a/cad/py-MyHDL/Makefile
+++ b/cad/py-MyHDL/Makefile
@@ -1,9 +1,8 @@
-# $NetBSD: Makefile,v 1.10 2006/02/05 23:08:22 joerg Exp $
+# $NetBSD: Makefile,v 1.11 2006/02/10 16:06:46 drochner Exp $
 #
 
-DISTNAME=	myhdl-0.4.1
-PKGNAME=	${PYPKGPREFIX}-MyHDL-0.4.1
-PKGREVISION=	1
+DISTNAME=	myhdl-0.5
+PKGNAME=	${PYPKGPREFIX}-MyHDL-0.5
 CATEGORIES=	cad python
 MASTER_SITES=	${MASTER_SITE_SOURCEFORGE:=myhdl/}
 
@@ -12,7 +11,10 @@ HOMEPAGE=	http://jandecaluwe.com/Tools/MyHDL/Overview.html
 COMMENT=	Hardware description in Python
 
 PYDISTUTILSPKG=	yes
-PYTHON_VERSIONS_ACCEPTED=	23 24
+PYTHON_VERSIONS_ACCEPTED=	24
+
+do-test:
+	cd ${WRKSRC}/myhdl/test && ${PYTHONBIN} test_all.py
 
 .include "../../lang/python/extension.mk"
 .include "../../mk/bsd.pkg.mk"
-- 
cgit v1.2.3