From 2530131eeb6aecddf50d12af618d56e0549d4bbb Mon Sep 17 00:00:00 2001 From: dmcmahill Date: Wed, 26 Jan 2000 15:28:40 +0000 Subject: Initial import of Icarus Verilog. Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal. I'll be tracking the upcoming IEEE Std 1364-1999 revision as well, and some -1999 features will creep in. --- cad/verilog/Makefile | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 cad/verilog/Makefile (limited to 'cad/verilog/Makefile') diff --git a/cad/verilog/Makefile b/cad/verilog/Makefile new file mode 100644 index 00000000000..b0f5bacca50 --- /dev/null +++ b/cad/verilog/Makefile @@ -0,0 +1,15 @@ +# $NetBSD: Makefile,v 1.1.1.1 2000/01/26 15:28:40 dmcmahill Exp $ +# + +DISTNAME= verilog-20000120 +CATEGORIES= cad +MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/ + +MAINTAINER= packages@netbsd.org +HOMEPAGE= http://icarus.com/eda/verilog/index.html + +BUILD_DEPENDS+= bison:../../devel/bison + +GNU_CONFIGURE= YES + +.include "../../mk/bsd.pkg.mk" -- cgit v1.2.3