From fe2c5b1c959ebd3e093365fef8f206c2761be4c0 Mon Sep 17 00:00:00 2001
From: dmcmahill <dmcmahill@pkgsrc.org>
Date: Sun, 15 Dec 2002 01:57:12 +0000
Subject: update to verilog-0.7

This release represents many bug fixes, expanded language coverage,
greatly enhanced xilinx fpga synthesis and several performance enhancements.
The complete list is rather long.
---
 cad/verilog/PLIST | 17 ++++++-----------
 1 file changed, 6 insertions(+), 11 deletions(-)

(limited to 'cad/verilog/PLIST')

diff --git a/cad/verilog/PLIST b/cad/verilog/PLIST
index 4d99fc6fae9..67766e16766 100644
--- a/cad/verilog/PLIST
+++ b/cad/verilog/PLIST
@@ -1,19 +1,13 @@
-@comment $NetBSD: PLIST,v 1.2 2002/02/08 01:48:32 dmcmahill Exp $
+@comment $NetBSD: PLIST,v 1.3 2002/12/15 01:57:12 dmcmahill Exp $
 bin/iverilog
+bin/iverilog-vpi
 bin/vvp
+include/acc_user.h
 include/ivl_target.h
-include/vpi_priv.h
+include/veriuser.h
 include/vpi_user.h
-include/vvm.h
-include/vvm_calltf.h
-include/vvm_func.h
-include/vvm_gates.h
-include/vvm_nexus.h
-include/vvm_signal.h
-include/vvm_thread.h
+lib/libveriuser.a
 lib/libvpi.a
-lib/libvpip.a
-lib/libvvm.a
 lib/ivl/fpga.tgt
 lib/ivl/ivl
 lib/ivl/iverilog.conf
@@ -22,5 +16,6 @@ lib/ivl/null.tgt
 lib/ivl/system.vpi
 lib/ivl/vvp.tgt
 man/man1/iverilog.1
+man/man1/iverilog-vpi.1
 man/man1/vvp.1
 @dirrm lib/ivl
-- 
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