From 09a3687c308a64581029d15526192b5aa4052fc7 Mon Sep 17 00:00:00 2001
From: jnemeth <jnemeth>
Date: Thu, 13 Oct 2016 04:10:16 +0000
Subject: verilog is no longer

---
 cad/Makefile | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'cad')

diff --git a/cad/Makefile b/cad/Makefile
index c568146736e..0df3829a89b 100644
--- a/cad/Makefile
+++ b/cad/Makefile
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile,v 1.91 2016/10/09 13:15:03 kamil Exp $
+# $NetBSD: Makefile,v 1.92 2016/10/13 04:10:16 jnemeth Exp $
 #
 
 COMMENT=	CAD tools
@@ -62,7 +62,6 @@ SUBDIR+=	stdio-wcalc
 SUBDIR+=	tkgate
 SUBDIR+=	tnt-mmtl
 SUBDIR+=	transcalc
-SUBDIR+=	verilog
 SUBDIR+=	verilog-mode
 SUBDIR+=	veriwell
 SUBDIR+=	vipec
-- 
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