From 0a88f2ddc619626e67e68b99917638b37e5a56c7 Mon Sep 17 00:00:00 2001 From: cjep Date: Tue, 30 Dec 2003 22:55:04 +0000 Subject: Whitespace fix --- cad/verilog-current/buildlink2.mk | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'cad') diff --git a/cad/verilog-current/buildlink2.mk b/cad/verilog-current/buildlink2.mk index e82db3c9772..17d03d273cb 100644 --- a/cad/verilog-current/buildlink2.mk +++ b/cad/verilog-current/buildlink2.mk @@ -1,4 +1,4 @@ -# $NetBSD: buildlink2.mk,v 1.1 2002/11/10 01:57:48 dmcmahill Exp $ +# $NetBSD: buildlink2.mk,v 1.2 2003/12/30 22:55:58 cjep Exp $ # # This Makefile fragment is included by packages that use verilog-current. # @@ -28,7 +28,6 @@ BUILDLINK_FILES.verilog-current+= lib/ivl/vvp.tgt BUILDLINK_FILES.verilog-current+= lib/libveriuser.* BUILDLINK_FILES.verilog-current+= lib/libvpi.* - BUILDLINK_TARGETS+= verilog-current-buildlink verilog-current-buildlink: _BUILDLINK_USE -- cgit v1.2.3