From 0d073fb36fe0af12787bd28f78d90f7d18ed5f56 Mon Sep 17 00:00:00 2001
From: kamil <kamil>
Date: Sat, 8 Oct 2016 23:11:23 +0000
Subject: Switch from cad/verilog to cad/iverilog

Bump PKGREVISION to 1.
---
 cad/MyHDL-iverilog/Makefile | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'cad')

diff --git a/cad/MyHDL-iverilog/Makefile b/cad/MyHDL-iverilog/Makefile
index 939c14aa26f..22584367e3b 100644
--- a/cad/MyHDL-iverilog/Makefile
+++ b/cad/MyHDL-iverilog/Makefile
@@ -1,8 +1,9 @@
-# $NetBSD: Makefile,v 1.8 2015/01/04 02:45:50 mef Exp $
+# $NetBSD: Makefile,v 1.9 2016/10/08 23:11:23 kamil Exp $
 #
 
 DISTNAME=	myhdl-0.8.1
 PKGNAME=	MyHDL-iverilog-0.7
+PKGREVISION=	1
 PKGNAME=	${DISTNAME:C/myhdl/MyHDL-iverilog/}
 CATEGORIES=	cad python
 MASTER_SITES=	${MASTER_SITE_SOURCEFORGE:=myhdl/}
@@ -23,5 +24,5 @@ do-install:
 #do-test:
 #	(cd ${WRKSRC}/cosimulation/icarus/test && ${PYTHONBIN} test_all.py)
 
-.include "../../cad/verilog/buildlink3.mk"
+.include "../../cad/iverilog/buildlink3.mk"
 .include "../../mk/bsd.pkg.mk"
-- 
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