From 4ca0722c59c3c3cc367a0360212dba8a64731f44 Mon Sep 17 00:00:00 2001
From: drochner <drochner@pkgsrc.org>
Date: Fri, 10 Feb 2006 16:06:46 +0000
Subject: update to 0.5 major changes: -supports Python decorator syntax for
 generators (needs 2.4) -intbv() doesn't have a default anymore -many
 improvements to Verilog conversion

---
 cad/py-MyHDL/Makefile | 12 +++++++-----
 cad/py-MyHDL/PLIST    | 11 ++++++++++-
 cad/py-MyHDL/distinfo |  8 ++++----
 3 files changed, 21 insertions(+), 10 deletions(-)

(limited to 'cad')

diff --git a/cad/py-MyHDL/Makefile b/cad/py-MyHDL/Makefile
index 53590f6a464..56398018e7d 100644
--- a/cad/py-MyHDL/Makefile
+++ b/cad/py-MyHDL/Makefile
@@ -1,9 +1,8 @@
-# $NetBSD: Makefile,v 1.10 2006/02/05 23:08:22 joerg Exp $
+# $NetBSD: Makefile,v 1.11 2006/02/10 16:06:46 drochner Exp $
 #
 
-DISTNAME=	myhdl-0.4.1
-PKGNAME=	${PYPKGPREFIX}-MyHDL-0.4.1
-PKGREVISION=	1
+DISTNAME=	myhdl-0.5
+PKGNAME=	${PYPKGPREFIX}-MyHDL-0.5
 CATEGORIES=	cad python
 MASTER_SITES=	${MASTER_SITE_SOURCEFORGE:=myhdl/}
 
@@ -12,7 +11,10 @@ HOMEPAGE=	http://jandecaluwe.com/Tools/MyHDL/Overview.html
 COMMENT=	Hardware description in Python
 
 PYDISTUTILSPKG=	yes
-PYTHON_VERSIONS_ACCEPTED=	23 24
+PYTHON_VERSIONS_ACCEPTED=	24
+
+do-test:
+	cd ${WRKSRC}/myhdl/test && ${PYTHONBIN} test_all.py
 
 .include "../../lang/python/extension.mk"
 .include "../../mk/bsd.pkg.mk"
diff --git a/cad/py-MyHDL/PLIST b/cad/py-MyHDL/PLIST
index 89d54ecf890..e2b0d1b1eb4 100644
--- a/cad/py-MyHDL/PLIST
+++ b/cad/py-MyHDL/PLIST
@@ -1,4 +1,4 @@
-@comment $NetBSD: PLIST,v 1.3 2005/01/05 15:20:10 drochner Exp $
+@comment $NetBSD: PLIST,v 1.4 2006/02/10 16:06:46 drochner Exp $
 ${PYSITELIB}/myhdl/_Cosimulation.py
 ${PYSITELIB}/myhdl/_Cosimulation.pyc
 ${PYSITELIB}/myhdl/_Cosimulation.pyo
@@ -14,6 +14,9 @@ ${PYSITELIB}/myhdl/_Waiter.pyo
 ${PYSITELIB}/myhdl/__init__.py
 ${PYSITELIB}/myhdl/__init__.pyc
 ${PYSITELIB}/myhdl/__init__.pyo
+${PYSITELIB}/myhdl/_always.py
+${PYSITELIB}/myhdl/_always.pyc
+${PYSITELIB}/myhdl/_always.pyo
 ${PYSITELIB}/myhdl/_always_comb.py
 ${PYSITELIB}/myhdl/_always_comb.pyc
 ${PYSITELIB}/myhdl/_always_comb.pyo
@@ -35,6 +38,9 @@ ${PYSITELIB}/myhdl/_enum.pyo
 ${PYSITELIB}/myhdl/_extractHierarchy.py
 ${PYSITELIB}/myhdl/_extractHierarchy.pyc
 ${PYSITELIB}/myhdl/_extractHierarchy.pyo
+${PYSITELIB}/myhdl/_instance.py
+${PYSITELIB}/myhdl/_instance.pyc
+${PYSITELIB}/myhdl/_instance.pyo
 ${PYSITELIB}/myhdl/_intbv.py
 ${PYSITELIB}/myhdl/_intbv.pyc
 ${PYSITELIB}/myhdl/_intbv.pyo
@@ -68,5 +74,8 @@ ${PYSITELIB}/myhdl/_unparse.pyo
 ${PYSITELIB}/myhdl/_util.py
 ${PYSITELIB}/myhdl/_util.pyc
 ${PYSITELIB}/myhdl/_util.pyo
+${PYSITELIB}/myhdl/test.py
+${PYSITELIB}/myhdl/test.pyc
+${PYSITELIB}/myhdl/test.pyo
 @dirrm ${PYSITELIB}/myhdl/_toVerilog
 @dirrm ${PYSITELIB}/myhdl
diff --git a/cad/py-MyHDL/distinfo b/cad/py-MyHDL/distinfo
index 1e2bc5f81d3..cf392e2fb73 100644
--- a/cad/py-MyHDL/distinfo
+++ b/cad/py-MyHDL/distinfo
@@ -1,5 +1,5 @@
-$NetBSD: distinfo,v 1.3 2005/02/23 14:59:25 agc Exp $
+$NetBSD: distinfo,v 1.4 2006/02/10 16:06:46 drochner Exp $
 
-SHA1 (myhdl-0.4.1.tar.gz) = 84096c83351152b1354a331a0b8c3c1bf4098dde
-RMD160 (myhdl-0.4.1.tar.gz) = 237995b0ef44653a43ca478b163a3512f59d5e7c
-Size (myhdl-0.4.1.tar.gz) = 1205572 bytes
+SHA1 (myhdl-0.5.tar.gz) = c97517d7b70d6e4a56f6a2576baa685d53c394d3
+RMD160 (myhdl-0.5.tar.gz) = 2cbc89c5c2bd61a636b64bf5654471900f940ffc
+Size (myhdl-0.5.tar.gz) = 759071 bytes
-- 
cgit v1.2.3