From 6de823231a819ec0abcbc9a4b91d2a60e1e70b05 Mon Sep 17 00:00:00 2001
From: joerg <joerg@pkgsrc.org>
Date: Fri, 29 Nov 2013 12:53:45 +0000
Subject: Has race conditions during build.

---
 cad/verilog-current/Makefile | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

(limited to 'cad')

diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile
index df1fe56c354..c0247462aac 100644
--- a/cad/verilog-current/Makefile
+++ b/cad/verilog-current/Makefile
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile,v 1.59 2013/07/15 02:02:18 ryoon Exp $
+# $NetBSD: Makefile,v 1.60 2013/11/29 12:53:45 joerg Exp $
 #
 
 DISTNAME=	verilog-${SNAPDATE}
@@ -12,6 +12,11 @@ HOMEPAGE=	http://icarus.com/eda/verilog/index.html
 COMMENT=	Verilog simulation and synthesis tool (development snapshot version)
 LICENSE=	gnu-gpl-v2
 
+# In driver:
+# mkdir: dep: Not a directory
+# Makefile:76: recipe for target 'dep' failed
+MAKE_JOBS_SAFE=	no
+
 PKG_INSTALLATION_TYPES=	overwrite pkgviews
 
 CONFLICTS+=	verilog-[0-9]*
-- 
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