From aa2c18597030da0d965f6ed3215672811747d22a Mon Sep 17 00:00:00 2001
From: kamil <kamil>
Date: Sun, 9 Oct 2016 13:15:03 +0000
Subject: Add cad/veriwell

---
 cad/Makefile | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'cad')

diff --git a/cad/Makefile b/cad/Makefile
index eeeec871e98..c568146736e 100644
--- a/cad/Makefile
+++ b/cad/Makefile
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile,v 1.90 2016/10/08 23:07:02 kamil Exp $
+# $NetBSD: Makefile,v 1.91 2016/10/09 13:15:03 kamil Exp $
 #
 
 COMMENT=	CAD tools
@@ -64,6 +64,7 @@ SUBDIR+=	tnt-mmtl
 SUBDIR+=	transcalc
 SUBDIR+=	verilog
 SUBDIR+=	verilog-mode
+SUBDIR+=	veriwell
 SUBDIR+=	vipec
 SUBDIR+=	wcalc
 SUBDIR+=	wcalc-docs
-- 
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