From afeee422eec52f3c27ed44deede153bb0af34b01 Mon Sep 17 00:00:00 2001
From: drochner <drochner>
Date: Fri, 10 Feb 2006 16:40:02 +0000
Subject: import MyHDL-gplcver-0.5, a GPL Cver vpi module to support
 cosimulation from py-MyHDL

---
 cad/MyHDL-gplcver/DESCR            |  7 +++++++
 cad/MyHDL-gplcver/Makefile         | 21 +++++++++++++++++++++
 cad/MyHDL-gplcver/PLIST            |  2 ++
 cad/MyHDL-gplcver/distinfo         |  6 ++++++
 cad/MyHDL-gplcver/patches/patch-aa | 13 +++++++++++++
 5 files changed, 49 insertions(+)
 create mode 100644 cad/MyHDL-gplcver/DESCR
 create mode 100644 cad/MyHDL-gplcver/Makefile
 create mode 100644 cad/MyHDL-gplcver/PLIST
 create mode 100644 cad/MyHDL-gplcver/distinfo
 create mode 100644 cad/MyHDL-gplcver/patches/patch-aa

(limited to 'cad')

diff --git a/cad/MyHDL-gplcver/DESCR b/cad/MyHDL-gplcver/DESCR
new file mode 100644
index 00000000000..fd819237dc9
--- /dev/null
+++ b/cad/MyHDL-gplcver/DESCR
@@ -0,0 +1,7 @@
+MyHDL is a Python package for using Python as a hardware
+description language. Popular hardware description languages, like
+Verilog and VHDL, are compiled languages. MyHDL with Python
+can be viewed as a "scripting language" counterpart of such
+languages. However, Python is more accurately described as a very
+high level language (VHLL). MyHDL users have access to the
+amazing power and elegance of Python for their modeling work.
diff --git a/cad/MyHDL-gplcver/Makefile b/cad/MyHDL-gplcver/Makefile
new file mode 100644
index 00000000000..f49104da8d8
--- /dev/null
+++ b/cad/MyHDL-gplcver/Makefile
@@ -0,0 +1,21 @@
+# $NetBSD: Makefile,v 1.1.1.1 2006/02/10 16:40:02 drochner Exp $
+#
+
+DISTNAME=	myhdl-0.5
+PKGNAME=	MyHDL-gplcver-0.5
+CATEGORIES=	cad python
+MASTER_SITES=	${MASTER_SITE_SOURCEFORGE:=myhdl/}
+
+MAINTAINER=	tech-pkg@NetBSD.org
+HOMEPAGE=	http://jandecaluwe.com/Tools/MyHDL/Overview.html
+COMMENT=	GPL Cver cosimulation support for py-MyHDL
+
+BUILD_DIRS+=	cosimulation/cver
+MAKEFILE=	makefile.lnx
+
+do-install:
+	${INSTALL_DATA} ${WRKSRC}/cosimulation/cver/myhdl_vpi.so \
+		${PREFIX}/lib/gplcver
+
+.include "../../cad/gplcver/buildlink3.mk"
+.include "../../mk/bsd.pkg.mk"
diff --git a/cad/MyHDL-gplcver/PLIST b/cad/MyHDL-gplcver/PLIST
new file mode 100644
index 00000000000..1e3a7421c93
--- /dev/null
+++ b/cad/MyHDL-gplcver/PLIST
@@ -0,0 +1,2 @@
+@comment $NetBSD: PLIST,v 1.1.1.1 2006/02/10 16:40:02 drochner Exp $
+lib/gplcver/myhdl_vpi.so
diff --git a/cad/MyHDL-gplcver/distinfo b/cad/MyHDL-gplcver/distinfo
new file mode 100644
index 00000000000..3b2d408e64c
--- /dev/null
+++ b/cad/MyHDL-gplcver/distinfo
@@ -0,0 +1,6 @@
+$NetBSD: distinfo,v 1.1.1.1 2006/02/10 16:40:02 drochner Exp $
+
+SHA1 (myhdl-0.5.tar.gz) = c97517d7b70d6e4a56f6a2576baa685d53c394d3
+RMD160 (myhdl-0.5.tar.gz) = 2cbc89c5c2bd61a636b64bf5654471900f940ffc
+Size (myhdl-0.5.tar.gz) = 759071 bytes
+SHA1 (patch-aa) = bb11bc3fed7b77c9b50108e92e65c972734a43fd
diff --git a/cad/MyHDL-gplcver/patches/patch-aa b/cad/MyHDL-gplcver/patches/patch-aa
new file mode 100644
index 00000000000..98dfedc68da
--- /dev/null
+++ b/cad/MyHDL-gplcver/patches/patch-aa
@@ -0,0 +1,13 @@
+$NetBSD: patch-aa,v 1.1.1.1 2006/02/10 16:40:02 drochner Exp $
+
+--- cosimulation/cver/makefile.lnx.orig	2006-02-10 17:20:16.000000000 +0100
++++ cosimulation/cver/makefile.lnx
+@@ -2,7 +2,7 @@
+ WARNS=-Wall
+ 
+ # change this path to point to the pli include files directory for cver
+-INCS=-I$(HOME)/gplcver-2.11a.src/pli_incs
++INCS=-I$(LOCALBASE)/lib/gplcver/pli_incs
+ # maybe want -O<something> and/or -g
+ CFLAGS= -fPIC -Wall -g $(INCS)
+ LFLAGS= -G -shared -export-dynamic
-- 
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