From c9882b4cabf2245cacd495e5c35cef6b792d2ffc Mon Sep 17 00:00:00 2001
From: kamil <kamil>
Date: Sun, 9 Oct 2016 13:14:06 +0000
Subject: Import veriwell-2.8.7 as cad/veriwell

VeriWell is a full Verilog simulator. It supports nearly all of the
IEEE1364-1995 standard, as well as PLI 1.0.

Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in
the mid-1990 and was included with the Thomas and Moorby book.
---
 cad/veriwell/DESCR    |  5 +++++
 cad/veriwell/Makefile | 18 ++++++++++++++++++
 cad/veriwell/PLIST    |  7 +++++++
 cad/veriwell/distinfo |  6 ++++++
 4 files changed, 36 insertions(+)
 create mode 100644 cad/veriwell/DESCR
 create mode 100644 cad/veriwell/Makefile
 create mode 100644 cad/veriwell/PLIST
 create mode 100644 cad/veriwell/distinfo

(limited to 'cad')

diff --git a/cad/veriwell/DESCR b/cad/veriwell/DESCR
new file mode 100644
index 00000000000..0bb0f68989b
--- /dev/null
+++ b/cad/veriwell/DESCR
@@ -0,0 +1,5 @@
+VeriWell is a full Verilog simulator. It supports nearly all of the
+IEEE1364-1995 standard, as well as PLI 1.0.
+
+Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in
+the mid-1990 and was included with the Thomas and Moorby book.
diff --git a/cad/veriwell/Makefile b/cad/veriwell/Makefile
new file mode 100644
index 00000000000..05b505ccbba
--- /dev/null
+++ b/cad/veriwell/Makefile
@@ -0,0 +1,18 @@
+# $NetBSD: Makefile,v 1.1 2016/10/09 13:14:06 kamil Exp $
+
+DISTNAME=	veriwell-2.8.7
+CATEGORIES=	cad
+MASTER_SITES=	${MASTER_SITE_SOURCEFORGE:=veriwell/}
+
+MAINTAINER=	pkgsrc-users@NetBSD.org
+HOMEPAGE=	https://sourceforge.net/projects/veriwell/
+COMMENT=	Verilog Simulator
+LICENSE=	gnu-gpl-v2
+
+GNU_CONFIGURE=	yes
+USE_LANGUAGES=	c c++
+
+TEST_TARGET=	check
+
+.include "../../devel/zlib/buildlink3.mk"
+.include "../../mk/bsd.pkg.mk"
diff --git a/cad/veriwell/PLIST b/cad/veriwell/PLIST
new file mode 100644
index 00000000000..b80b73c062e
--- /dev/null
+++ b/cad/veriwell/PLIST
@@ -0,0 +1,7 @@
+@comment $NetBSD: PLIST,v 1.1 2016/10/09 13:14:06 kamil Exp $
+bin/veriwell
+include/acc_user.h
+include/veriuser.c
+include/veriuser.h
+lib/libveriwell.la
+man/man1/veriwell.1
diff --git a/cad/veriwell/distinfo b/cad/veriwell/distinfo
new file mode 100644
index 00000000000..59ab4c5c7c8
--- /dev/null
+++ b/cad/veriwell/distinfo
@@ -0,0 +1,6 @@
+$NetBSD: distinfo,v 1.1 2016/10/09 13:14:06 kamil Exp $
+
+SHA1 (veriwell-2.8.7.tar.gz) = 9ef4e6a25a4fd65db325a89ed89b199547fabbd6
+RMD160 (veriwell-2.8.7.tar.gz) = 3d86c40b353f701d61cab301e0f7c3ec136c88e7
+SHA512 (veriwell-2.8.7.tar.gz) = c0858ce71bd8cfef989e96899bc0d5fc0c919d8248cad0bebde7faf31073cde0423ddb168cf0fabb9f7b46ced7b953ad392627b7e1ad5ea1e7ef75f9524717a8
+Size (veriwell-2.8.7.tar.gz) = 875596 bytes
-- 
cgit v1.2.3