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share/uhd/fpga/usrp3/top/x300/coregen/pcie_clk_gen/simulation/timing/simulate_mti.bat share/uhd/fpga/usrp3/top/x300/coregen/pcie_clk_gen/simulation/timing/simulate_mti.do share/uhd/fpga/usrp3/top/x300/coregen/pcie_clk_gen/simulation/timing/simulate_mti.sh share/uhd/fpga/usrp3/top/x300/coregen/pcie_clk_gen/simulation/timing/simulate_ncsim.sh share/uhd/fpga/usrp3/top/x300/coregen/pcie_clk_gen/simulation/timing/simulate_vcs.sh share/uhd/fpga/usrp3/top/x300/coregen/pcie_clk_gen/simulation/timing/ucli_commands.key share/uhd/fpga/usrp3/top/x300/coregen/pcie_clk_gen/simulation/timing/vcs_session.tcl share/uhd/fpga/usrp3/top/x300/coregen/pcie_clk_gen/simulation/timing/wave.do share/uhd/fpga/usrp3/top/x300/coregen/pcie_clk_gen_flist.txt share/uhd/fpga/usrp3/top/x300/coregen/pcie_clk_gen_xmdf.tcl share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen.asy share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen.gise share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen.ucf 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share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/implement/implement.sh share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/implement/planAhead_ise.bat share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/implement/planAhead_ise.sh share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/implement/planAhead_ise.tcl share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/implement/planAhead_rdn.bat share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/implement/planAhead_rdn.sh share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/implement/planAhead_rdn.tcl share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/implement/xst.prj share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/implement/xst.scr share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/functional/simcmds.tcl share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/functional/simulate_isim.bat share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/functional/simulate_isim.sh share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/functional/simulate_mti.bat share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/functional/simulate_mti.do share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/functional/simulate_mti.sh share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/functional/simulate_ncsim.sh share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/functional/simulate_vcs.sh share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/functional/ucli_commands.key share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/functional/vcs_session.tcl share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/functional/wave.do share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/functional/wave.sv share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/radio_clk_gen_tb.v share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/timing/radio_clk_gen_tb.v share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/timing/sdf_cmd_file share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/timing/simcmds.tcl share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/timing/simulate_isim.sh share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/timing/simulate_mti.bat share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/timing/simulate_mti.do share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/timing/simulate_mti.sh share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/timing/simulate_ncsim.sh share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/timing/simulate_vcs.sh share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/timing/ucli_commands.key share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/timing/vcs_session.tcl share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen/simulation/timing/wave.do share/uhd/fpga/usrp3/top/x300/coregen/radio_clk_gen_exdes.ncf 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share/uhd/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/implement/implement.sh share/uhd/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/implement/ten_gig_eth_pcs_pma_example_design.xcf share/uhd/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/implement/xst.prj share/uhd/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/implement/xst.scr share/uhd/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/simulation/demo_tb.v share/uhd/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/simulation/functional/simulate_mti.do share/uhd/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/simulation/functional/simulate_ncsim.sh share/uhd/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/simulation/functional/simulate_vcs.sh share/uhd/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/simulation/functional/ucli_commands.key share/uhd/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/simulation/functional/vcs_session.tcl share/uhd/fpga/usrp3/top/x300/coregen/ten_gig_eth_pcs_pma/simulation/functional/wave_mti.do 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