summaryrefslogtreecommitdiff
path: root/cad/verilog-current
ModeNameSize
-rw-r--r--DESCR968logplain
-rw-r--r--Makefile957logplain
-rw-r--r--PLIST486logplain
-rw-r--r--distinfo240logplain
d---------patches36logplain
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-20 21:25:53 +0000