Imported Upstream version 4.2-build2006upstream/4.2-build2006upstream

7 files changed, 7111 insertions, 0 deletions

diff --git a/kernel/drv/oss_cs461x/.devices b/kernel/drv/oss_cs461x/.devices
new file mode 100644
index 0000000..2ee1e6f
--- /dev/null
+++ b/kernel/drv/oss_cs461x/.devices
@@ -0,0 +1,7 @@
+oss_cs461x	pci1013,6001	Crystal CS4610
+oss_cs461x	pci1013,6003	Crystal CS4280 
+oss_cs461x	pci1013,6004	Crystal CS4615
+oss_cs461x	pcs153b,112e	Terratec DMX Xfire 1024
+oss_cs461x	pcs1681,50	Hercules Game Theater XP
+oss_cs461x	pcs1681,51	Hercules Game Theater XP+
+oss_cs461x	pcs5053,3357	TurtleBeach SantaCruz / VideoLogic SonicFury
diff --git a/kernel/drv/oss_cs461x/.name b/kernel/drv/oss_cs461x/.name
new file mode 100644
index 0000000..3c0e69b
--- /dev/null
+++ b/kernel/drv/oss_cs461x/.name
@@ -0,0 +1 @@
+Crystal CS461x/CS4280
diff --git a/kernel/drv/oss_cs461x/.params b/kernel/drv/oss_cs461x/.params
new file mode 100644
index 0000000..18ed0a3
--- /dev/null
+++ b/kernel/drv/oss_cs461x/.params
@@ -0,0 +1,6 @@
+int cs461x_clkrun_fix=0;
+/*
+ * Some IBM Thinkpads require a workaround for the CLKRUN protocol. 
+ * Values: 1=Enable 0=Disable  Default: 0
+ */
+
diff --git a/kernel/drv/oss_cs461x/cs461x.h b/kernel/drv/oss_cs461x/cs461x.h
new file mode 100644
index 0000000..79ae7f5
--- /dev/null
+++ b/kernel/drv/oss_cs461x/cs461x.h
@@ -0,0 +1,1668 @@
+/*
+ * Purpose: Definitions for the cs461x driver
+ */
+/*
+ *
+ * This file is part of Open Sound System.
+ *
+ * Copyright (C) 4Front Technologies 1996-2008.
+ *
+ * This this source file is released under GPL v2 license (no other versions).
+ * See the COPYING file included in the main directory of this source
+ * distribution for the license terms and conditions.
+ *
+ */
+
+
+/*
+ *  Direct registers
+ */
+
+/*
+ *  The following define the offsets of the registers accessed via base address
+ *  register zero on the CS461x part.
+ */
+#define BA0_HISR				0x00000000
+#define BA0_HSR0                                0x00000004
+#define BA0_HICR                                0x00000008
+#define BA0_DMSR                                0x00000100
+#define BA0_HSAR                                0x00000110
+#define BA0_HDAR                                0x00000114
+#define BA0_HDMR                                0x00000118
+#define BA0_HDCR                                0x0000011C
+#define BA0_PFMC                                0x00000200
+#define BA0_PFCV1                               0x00000204
+#define BA0_PFCV2                               0x00000208
+#define BA0_PCICFG00                            0x00000300
+#define BA0_PCICFG04                            0x00000304
+#define BA0_PCICFG08                            0x00000308
+#define BA0_PCICFG0C                            0x0000030C
+#define BA0_PCICFG10                            0x00000310
+#define BA0_PCICFG14                            0x00000314
+#define BA0_PCICFG18                            0x00000318
+#define BA0_PCICFG1C                            0x0000031C
+#define BA0_PCICFG20                            0x00000320
+#define BA0_PCICFG24                            0x00000324
+#define BA0_PCICFG28                            0x00000328
+#define BA0_PCICFG2C                            0x0000032C
+#define BA0_PCICFG30                            0x00000330
+#define BA0_PCICFG34                            0x00000334
+#define BA0_PCICFG38                            0x00000338
+#define BA0_PCICFG3C                            0x0000033C
+#define BA0_CLKCR1                              0x00000400
+#define BA0_CLKCR2                              0x00000404
+#define BA0_PLLM                                0x00000408
+#define BA0_PLLCC                               0x0000040C
+#define BA0_FRR                                 0x00000410
+#define BA0_CFL1                                0x00000414
+#define BA0_CFL2                                0x00000418
+#define BA0_SERMC1                              0x00000420
+#define BA0_SERMC2                              0x00000424
+#define BA0_SERC1                               0x00000428
+#define BA0_SERC2                               0x0000042C
+#define BA0_SERC3                               0x00000430
+#define BA0_SERC4                               0x00000434
+#define BA0_SERC5                               0x00000438
+#define BA0_SERBSP                              0x0000043C
+#define BA0_SERBST                              0x00000440
+#define BA0_SERBCM                              0x00000444
+#define BA0_SERBAD                              0x00000448
+#define BA0_SERBCF                              0x0000044C
+#define BA0_SERBWP                              0x00000450
+#define BA0_SERBRP                              0x00000454
+#ifndef NO_CS4612
+#define BA0_ASER_FADDR                          0x00000458
+#endif
+#define BA0_ACCTL                               0x00000460
+#define BA0_ACSTS                               0x00000464
+#define BA0_ACOSV                               0x00000468
+#define BA0_ACCAD                               0x0000046C
+#define BA0_ACCDA                               0x00000470
+#define BA0_ACISV                               0x00000474
+#define BA0_ACSAD                               0x00000478
+#define BA0_ACSDA                               0x0000047C
+#define BA0_JSPT                                0x00000480
+#define BA0_JSCTL                               0x00000484
+#define BA0_JSC1                                0x00000488
+#define BA0_JSC2                                0x0000048C
+#define BA0_MIDCR                               0x00000490
+#define BA0_MIDSR                               0x00000494
+#define BA0_MIDWP                               0x00000498
+#define BA0_MIDRP                               0x0000049C
+#define BA0_JSIO                                0x000004A0
+#ifndef NO_CS4612
+#define BA0_ASER_MASTER                         0x000004A4
+#endif
+#define BA0_CFGI                                0x000004B0
+#define BA0_SSVID                               0x000004B4
+#define BA0_GPIOR                               0x000004B8
+#ifndef NO_CS4612
+#define BA0_EGPIODR                             0x000004BC
+#define BA0_EGPIOPTR                            0x000004C0
+#define BA0_EGPIOTR                             0x000004C4
+#define BA0_EGPIOWR                             0x000004C8
+#define BA0_EGPIOSR                             0x000004CC
+#define BA0_SERC6                               0x000004D0
+#define BA0_SERC7                               0x000004D4
+#define BA0_SERACC                              0x000004D8
+#define BA0_ACCTL2                              0x000004E0
+#define BA0_ACSTS2                              0x000004E4
+#define BA0_ACOSV2                              0x000004E8
+#define BA0_ACCAD2                              0x000004EC
+#define BA0_ACCDA2                              0x000004F0
+#define BA0_ACISV2                              0x000004F4
+#define BA0_ACSAD2                              0x000004F8
+#define BA0_ACSDA2                              0x000004FC
+#define BA0_IOTAC0                              0x00000500
+#define BA0_IOTAC1                              0x00000504
+#define BA0_IOTAC2                              0x00000508
+#define BA0_IOTAC3                              0x0000050C
+#define BA0_IOTAC4                              0x00000510
+#define BA0_IOTAC5                              0x00000514
+#define BA0_IOTAC6                              0x00000518
+#define BA0_IOTAC7                              0x0000051C
+#define BA0_IOTAC8                              0x00000520
+#define BA0_IOTAC9                              0x00000524
+#define BA0_IOTAC10                             0x00000528
+#define BA0_IOTAC11                             0x0000052C
+#define BA0_IOTFR0                              0x00000540
+#define BA0_IOTFR1                              0x00000544
+#define BA0_IOTFR2                              0x00000548
+#define BA0_IOTFR3                              0x0000054C
+#define BA0_IOTFR4                              0x00000550
+#define BA0_IOTFR5                              0x00000554
+#define BA0_IOTFR6                              0x00000558
+#define BA0_IOTFR7                              0x0000055C
+#define BA0_IOTFIFO                             0x00000580
+#define BA0_IOTRRD                              0x00000584
+#define BA0_IOTFP                               0x00000588
+#define BA0_IOTCR                               0x0000058C
+#define BA0_DPCID                               0x00000590
+#define BA0_DPCIA                               0x00000594
+#define BA0_DPCIC                               0x00000598
+#define BA0_PCPCIR                              0x00000600
+#define BA0_PCPCIG                              0x00000604
+#define BA0_PCPCIEN                             0x00000608
+#define BA0_EPCIPMC                             0x00000610
+#endif
+
+/*
+ *  The following define the offsets of the registers and memories accessed via
+ *  base address register one on the CS461x part.
+ */
+#define BA1_SP_DMEM0                            0x00000000
+#define BA1_SP_DMEM1                            0x00010000
+#define BA1_SP_PMEM                             0x00020000
+#define BA1_SP_REG				0x00030000
+#define BA1_SPCR                                0x00030000
+#define BA1_DREG                                0x00030004
+#define BA1_DSRWP                               0x00030008
+#define BA1_TWPR                                0x0003000C
+#define BA1_SPWR                                0x00030010
+#define BA1_SPIR                                0x00030014
+#define BA1_FGR1                                0x00030020
+#define BA1_SPCS                                0x00030028
+#define BA1_SDSR                                0x0003002C
+#define BA1_FRMT                                0x00030030
+#define BA1_FRCC                                0x00030034
+#define BA1_FRSC                                0x00030038
+#define BA1_OMNI_MEM                            0x000E0000
+
+/*
+ *  The following defines are for the flags in the host interrupt status
+ *  register.
+ */
+#define HISR_VC_MASK                            0x0000FFFF
+#define HISR_VC0                                0x00000001
+#define HISR_VC1                                0x00000002
+#define HISR_VC2                                0x00000004
+#define HISR_VC3                                0x00000008
+#define HISR_VC4                                0x00000010
+#define HISR_VC5                                0x00000020
+#define HISR_VC6                                0x00000040
+#define HISR_VC7                                0x00000080
+#define HISR_VC8                                0x00000100
+#define HISR_VC9                                0x00000200
+#define HISR_VC10                               0x00000400
+#define HISR_VC11                               0x00000800
+#define HISR_VC12                               0x00001000
+#define HISR_VC13                               0x00002000
+#define HISR_VC14                               0x00004000
+#define HISR_VC15                               0x00008000
+#define HISR_INT0                               0x00010000
+#define HISR_INT1                               0x00020000
+#define HISR_DMAI                               0x00040000
+#define HISR_FROVR                              0x00080000
+#define HISR_MIDI                               0x00100000
+#ifdef NO_CS4612
+#define HISR_RESERVED                           0x0FE00000
+#else
+#define HISR_SBINT                              0x00200000
+#define HISR_RESERVED                           0x0FC00000
+#endif
+#define HISR_H0P                                0x40000000
+#define HISR_INTENA                             0x80000000
+
+/*
+ *  The following defines are for the flags in the host signal register 0.
+ */
+#define HSR0_VC_MASK                            0xFFFFFFFF
+#define HSR0_VC16                               0x00000001
+#define HSR0_VC17                               0x00000002
+#define HSR0_VC18                               0x00000004
+#define HSR0_VC19                               0x00000008
+#define HSR0_VC20                               0x00000010
+#define HSR0_VC21                               0x00000020
+#define HSR0_VC22                               0x00000040
+#define HSR0_VC23                               0x00000080
+#define HSR0_VC24                               0x00000100
+#define HSR0_VC25                               0x00000200
+#define HSR0_VC26                               0x00000400
+#define HSR0_VC27                               0x00000800
+#define HSR0_VC28                               0x00001000
+#define HSR0_VC29                               0x00002000
+#define HSR0_VC30                               0x00004000
+#define HSR0_VC31                               0x00008000
+#define HSR0_VC32                               0x00010000
+#define HSR0_VC33                               0x00020000
+#define HSR0_VC34                               0x00040000
+#define HSR0_VC35                               0x00080000
+#define HSR0_VC36                               0x00100000
+#define HSR0_VC37                               0x00200000
+#define HSR0_VC38                               0x00400000
+#define HSR0_VC39                               0x00800000
+#define HSR0_VC40                               0x01000000
+#define HSR0_VC41                               0x02000000
+#define HSR0_VC42                               0x04000000
+#define HSR0_VC43                               0x08000000
+#define HSR0_VC44                               0x10000000
+#define HSR0_VC45                               0x20000000
+#define HSR0_VC46                               0x40000000
+#define HSR0_VC47                               0x80000000
+
+/*
+ *  The following defines are for the flags in the host interrupt control
+ *  register.
+ */
+#define HICR_IEV                                0x00000001
+#define HICR_CHGM                               0x00000002
+
+/*
+ *  The following defines are for the flags in the DMA status register.
+ */
+#define DMSR_HP                                 0x00000001
+#define DMSR_HR                                 0x00000002
+#define DMSR_SP                                 0x00000004
+#define DMSR_SR                                 0x00000008
+
+/*
+ *  The following defines are for the flags in the host DMA source address
+ *  register.
+ */
+#define HSAR_HOST_ADDR_MASK                     0xFFFFFFFF
+#define HSAR_DSP_ADDR_MASK                      0x0000FFFF
+#define HSAR_MEMID_MASK                         0x000F0000
+#define HSAR_MEMID_SP_DMEM0                     0x00000000
+#define HSAR_MEMID_SP_DMEM1                     0x00010000
+#define HSAR_MEMID_SP_PMEM                      0x00020000
+#define HSAR_MEMID_SP_DEBUG                     0x00030000
+#define HSAR_MEMID_OMNI_MEM                     0x000E0000
+#define HSAR_END                                0x40000000
+#define HSAR_ERR                                0x80000000
+
+/*
+ *  The following defines are for the flags in the host DMA destination address
+ *  register.
+ */
+#define HDAR_HOST_ADDR_MASK                     0xFFFFFFFF
+#define HDAR_DSP_ADDR_MASK                      0x0000FFFF
+#define HDAR_MEMID_MASK                         0x000F0000
+#define HDAR_MEMID_SP_DMEM0                     0x00000000
+#define HDAR_MEMID_SP_DMEM1                     0x00010000
+#define HDAR_MEMID_SP_PMEM                      0x00020000
+#define HDAR_MEMID_SP_DEBUG                     0x00030000
+#define HDAR_MEMID_OMNI_MEM                     0x000E0000
+#define HDAR_END                                0x40000000
+#define HDAR_ERR                                0x80000000
+
+/*
+ *  The following defines are for the flags in the host DMA control register.
+ */
+#define HDMR_AC_MASK                            0x0000F000
+#define HDMR_AC_8_16                            0x00001000
+#define HDMR_AC_M_S                             0x00002000
+#define HDMR_AC_B_L                             0x00004000
+#define HDMR_AC_S_U                             0x00008000
+
+/*
+ *  The following defines are for the flags in the host DMA control register.
+ */
+#define HDCR_COUNT_MASK                         0x000003FF
+#define HDCR_DONE                               0x00004000
+#define HDCR_OPT                                0x00008000
+#define HDCR_WBD                                0x00400000
+#define HDCR_WBS                                0x00800000
+#define HDCR_DMS_MASK                           0x07000000
+#define HDCR_DMS_LINEAR                         0x00000000
+#define HDCR_DMS_16_DWORDS                      0x01000000
+#define HDCR_DMS_32_DWORDS                      0x02000000
+#define HDCR_DMS_64_DWORDS                      0x03000000
+#define HDCR_DMS_128_DWORDS                     0x04000000
+#define HDCR_DMS_256_DWORDS                     0x05000000
+#define HDCR_DMS_512_DWORDS                     0x06000000
+#define HDCR_DMS_1024_DWORDS                    0x07000000
+#define HDCR_DH                                 0x08000000
+#define HDCR_SMS_MASK                           0x70000000
+#define HDCR_SMS_LINEAR                         0x00000000
+#define HDCR_SMS_16_DWORDS                      0x10000000
+#define HDCR_SMS_32_DWORDS                      0x20000000
+#define HDCR_SMS_64_DWORDS                      0x30000000
+#define HDCR_SMS_128_DWORDS                     0x40000000
+#define HDCR_SMS_256_DWORDS                     0x50000000
+#define HDCR_SMS_512_DWORDS                     0x60000000
+#define HDCR_SMS_1024_DWORDS                    0x70000000
+#define HDCR_SH                                 0x80000000
+#define HDCR_COUNT_SHIFT                        0
+
+/*
+ *  The following defines are for the flags in the performance monitor control
+ *  register.
+ */
+#define PFMC_C1SS_MASK                          0x0000001F
+#define PFMC_C1EV                               0x00000020
+#define PFMC_C1RS                               0x00008000
+#define PFMC_C2SS_MASK                          0x001F0000
+#define PFMC_C2EV                               0x00200000
+#define PFMC_C2RS                               0x80000000
+#define PFMC_C1SS_SHIFT                         0
+#define PFMC_C2SS_SHIFT                         16
+#define PFMC_BUS_GRANT                          0
+#define PFMC_GRANT_AFTER_REQ                    1
+#define PFMC_TRANSACTION                        2
+#define PFMC_DWORD_TRANSFER                     3
+#define PFMC_SLAVE_READ                         4
+#define PFMC_SLAVE_WRITE                        5
+#define PFMC_PREEMPTION                         6
+#define PFMC_DISCONNECT_RETRY                   7
+#define PFMC_INTERRUPT                          8
+#define PFMC_BUS_OWNERSHIP                      9
+#define PFMC_TRANSACTION_LAG                    10
+#define PFMC_PCI_CLOCK                          11
+#define PFMC_SERIAL_CLOCK                       12
+#define PFMC_SP_CLOCK                           13
+
+/*
+ *  The following defines are for the flags in the performance counter value 1
+ *  register.
+ */
+#define PFCV1_PC1V_MASK                         0xFFFFFFFF
+#define PFCV1_PC1V_SHIFT                        0
+
+/*
+ *  The following defines are for the flags in the performance counter value 2
+ *  register.
+ */
+#define PFCV2_PC2V_MASK                         0xFFFFFFFF
+#define PFCV2_PC2V_SHIFT                        0
+
+/*
+ *  The following defines are for the flags in the clock control register 1.
+ */
+#define CLKCR1_OSCS                             0x00000001
+#define CLKCR1_OSCP                             0x00000002
+#define CLKCR1_PLLSS_MASK                       0x0000000C
+#define CLKCR1_PLLSS_SERIAL                     0x00000000
+#define CLKCR1_PLLSS_CRYSTAL                    0x00000004
+#define CLKCR1_PLLSS_PCI                        0x00000008
+#define CLKCR1_PLLSS_RESERVED                   0x0000000C
+#define CLKCR1_PLLP                             0x00000010
+#define CLKCR1_SWCE                             0x00000020
+#define CLKCR1_PLLOS                            0x00000040
+
+/*
+ *  The following defines are for the flags in the clock control register 2.
+ */
+#define CLKCR2_PDIVS_MASK                       0x0000000F
+#define CLKCR2_PDIVS_1                          0x00000001
+#define CLKCR2_PDIVS_2                          0x00000002
+#define CLKCR2_PDIVS_4                          0x00000004
+#define CLKCR2_PDIVS_7                          0x00000007
+#define CLKCR2_PDIVS_8                          0x00000008
+#define CLKCR2_PDIVS_16                         0x00000000
+
+/*
+ *  The following defines are for the flags in the PLL multiplier register.
+ */
+#define PLLM_MASK                               0x000000FF
+#define PLLM_SHIFT                              0
+
+/*
+ *  The following defines are for the flags in the PLL capacitor coefficient
+ *  register.
+ */
+#define PLLCC_CDR_MASK                          0x00000007
+#ifndef NO_CS4610
+#define PLLCC_CDR_240_350_MHZ                   0x00000000
+#define PLLCC_CDR_184_265_MHZ                   0x00000001
+#define PLLCC_CDR_144_205_MHZ                   0x00000002
+#define PLLCC_CDR_111_160_MHZ                   0x00000003
+#define PLLCC_CDR_87_123_MHZ                    0x00000004
+#define PLLCC_CDR_67_96_MHZ                     0x00000005
+#define PLLCC_CDR_52_74_MHZ                     0x00000006
+#define PLLCC_CDR_45_58_MHZ                     0x00000007
+#endif
+#ifndef NO_CS4612
+#define PLLCC_CDR_271_398_MHZ                   0x00000000
+#define PLLCC_CDR_227_330_MHZ                   0x00000001
+#define PLLCC_CDR_167_239_MHZ                   0x00000002
+#define PLLCC_CDR_150_215_MHZ                   0x00000003
+#define PLLCC_CDR_107_154_MHZ                   0x00000004
+#define PLLCC_CDR_98_140_MHZ                    0x00000005
+#define PLLCC_CDR_73_104_MHZ                    0x00000006
+#define PLLCC_CDR_63_90_MHZ                     0x00000007
+#endif
+#define PLLCC_LPF_MASK                          0x000000F8
+#ifndef NO_CS4610
+#define PLLCC_LPF_23850_60000_KHZ               0x00000000
+#define PLLCC_LPF_7960_26290_KHZ                0x00000008
+#define PLLCC_LPF_4160_10980_KHZ                0x00000018
+#define PLLCC_LPF_1740_4580_KHZ                 0x00000038
+#define PLLCC_LPF_724_1910_KHZ                  0x00000078
+#define PLLCC_LPF_317_798_KHZ                   0x000000F8
+#endif
+#ifndef NO_CS4612
+#define PLLCC_LPF_25580_64530_KHZ               0x00000000
+#define PLLCC_LPF_14360_37270_KHZ               0x00000008
+#define PLLCC_LPF_6100_16020_KHZ                0x00000018
+#define PLLCC_LPF_2540_6690_KHZ                 0x00000038
+#define PLLCC_LPF_1050_2780_KHZ                 0x00000078
+#define PLLCC_LPF_450_1160_KHZ                  0x000000F8
+#endif
+
+/*
+ *  The following defines are for the flags in the feature reporting register.
+ */
+#define FRR_FAB_MASK                            0x00000003
+#define FRR_MASK_MASK                           0x0000001C
+#ifdef NO_CS4612
+#define FRR_CFOP_MASK                           0x000000E0
+#else
+#define FRR_CFOP_MASK                           0x00000FE0
+#endif
+#define FRR_CFOP_NOT_DVD                        0x00000020
+#define FRR_CFOP_A3D                            0x00000040
+#define FRR_CFOP_128_PIN                        0x00000080
+#ifndef NO_CS4612
+#define FRR_CFOP_CS4280                         0x00000800
+#endif
+#define FRR_FAB_SHIFT                           0
+#define FRR_MASK_SHIFT                          2
+#define FRR_CFOP_SHIFT                          5
+
+/*
+ *  The following defines are for the flags in the configuration load 1
+ *  register.
+ */
+#define CFL1_CLOCK_SOURCE_MASK                  0x00000003
+#define CFL1_CLOCK_SOURCE_CS423X                0x00000000
+#define CFL1_CLOCK_SOURCE_AC97                  0x00000001
+#define CFL1_CLOCK_SOURCE_CRYSTAL               0x00000002
+#define CFL1_CLOCK_SOURCE_DUAL_AC97             0x00000003
+#define CFL1_VALID_DATA_MASK                    0x000000FF
+
+/*
+ *  The following defines are for the flags in the configuration load 2
+ *  register.
+ */
+#define CFL2_VALID_DATA_MASK                    0x000000FF
+
+/*
+ *  The following defines are for the flags in the serial port master control
+ *  register 1.
+ */
+#define SERMC1_MSPE                             0x00000001
+#define SERMC1_PTC_MASK                         0x0000000E
+#define SERMC1_PTC_CS423X                       0x00000000
+#define SERMC1_PTC_AC97                         0x00000002
+#define SERMC1_PTC_DAC                          0x00000004
+#define SERMC1_PLB                              0x00000010
+#define SERMC1_XLB                              0x00000020
+
+/*
+ *  The following defines are for the flags in the serial port master control
+ *  register 2.
+ */
+#define SERMC2_LROE                             0x00000001
+#define SERMC2_MCOE                             0x00000002
+#define SERMC2_MCDIV                            0x00000004
+
+/*
+ *  The following defines are for the flags in the serial port 1 configuration
+ *  register.
+ */
+#define SERC1_SO1EN                             0x00000001
+#define SERC1_SO1F_MASK                         0x0000000E
+#define SERC1_SO1F_CS423X                       0x00000000
+#define SERC1_SO1F_AC97                         0x00000002
+#define SERC1_SO1F_DAC                          0x00000004
+#define SERC1_SO1F_SPDIF                        0x00000006
+
+/*
+ *  The following defines are for the flags in the serial port 2 configuration
+ *  register.
+ */
+#define SERC2_SI1EN                             0x00000001
+#define SERC2_SI1F_MASK                         0x0000000E
+#define SERC2_SI1F_CS423X                       0x00000000
+#define SERC2_SI1F_AC97                         0x00000002
+#define SERC2_SI1F_ADC                          0x00000004
+#define SERC2_SI1F_SPDIF                        0x00000006
+
+/*
+ *  The following defines are for the flags in the serial port 3 configuration
+ *  register.
+ */
+#define SERC3_SO2EN                             0x00000001
+#define SERC3_SO2F_MASK                         0x00000006
+#define SERC3_SO2F_DAC                          0x00000000
+#define SERC3_SO2F_SPDIF                        0x00000002
+
+/*
+ *  The following defines are for the flags in the serial port 4 configuration
+ *  register.
+ */
+#define SERC4_SO3EN                             0x00000001
+#define SERC4_SO3F_MASK                         0x00000006
+#define SERC4_SO3F_DAC                          0x00000000
+#define SERC4_SO3F_SPDIF                        0x00000002
+
+/*
+ *  The following defines are for the flags in the serial port 5 configuration
+ *  register.
+ */
+#define SERC5_SI2EN                             0x00000001
+#define SERC5_SI2F_MASK                         0x00000006
+#define SERC5_SI2F_ADC                          0x00000000
+#define SERC5_SI2F_SPDIF                        0x00000002
+
+/*
+ *  The following defines are for the flags in the serial port backdoor sample
+ *  pointer register.
+ */
+#define SERBSP_FSP_MASK                         0x0000000F
+#define SERBSP_FSP_SHIFT                        0
+
+/*
+ *  The following defines are for the flags in the serial port backdoor status
+ *  register.
+ */
+#define SERBST_RRDY                             0x00000001
+#define SERBST_WBSY                             0x00000002
+
+/*
+ *  The following defines are for the flags in the serial port backdoor command
+ *  register.
+ */
+#define SERBCM_RDC                              0x00000001
+#define SERBCM_WRC                              0x00000002
+
+/*
+ *  The following defines are for the flags in the serial port backdoor address
+ *  register.
+ */
+#ifdef NO_CS4612
+#define SERBAD_FAD_MASK                         0x000000FF
+#else
+#define SERBAD_FAD_MASK                         0x000001FF
+#endif
+#define SERBAD_FAD_SHIFT                        0
+
+/*
+ *  The following defines are for the flags in the serial port backdoor
+ *  configuration register.
+ */
+#define SERBCF_HBP                              0x00000001
+
+/*
+ *  The following defines are for the flags in the serial port backdoor write
+ *  port register.
+ */
+#define SERBWP_FWD_MASK                         0x000FFFFF
+#define SERBWP_FWD_SHIFT                        0
+
+/*
+ *  The following defines are for the flags in the serial port backdoor read
+ *  port register.
+ */
+#define SERBRP_FRD_MASK                         0x000FFFFF
+#define SERBRP_FRD_SHIFT                        0
+
+/*
+ *  The following defines are for the flags in the async FIFO address register.
+ */
+#ifndef NO_CS4612
+#define ASER_FADDR_A1_MASK                      0x000001FF
+#define ASER_FADDR_EN1                          0x00008000
+#define ASER_FADDR_A2_MASK                      0x01FF0000
+#define ASER_FADDR_EN2                          0x80000000
+#define ASER_FADDR_A1_SHIFT                     0
+#define ASER_FADDR_A2_SHIFT                     16
+#endif
+
+/*
+ *  The following defines are for the flags in the AC97 control register.
+ */
+#define ACCTL_RSTN                              0x00000001
+#define ACCTL_ESYN                              0x00000002
+#define ACCTL_VFRM                              0x00000004
+#define ACCTL_DCV                               0x00000008
+#define ACCTL_CRW                               0x00000010
+#define ACCTL_ASYN                              0x00000020
+#ifndef NO_CS4612
+#define ACCTL_TC                                0x00000040
+#endif
+
+/*
+ *  The following defines are for the flags in the AC97 status register.
+ */
+#define ACSTS_CRDY                              0x00000001
+#define ACSTS_VSTS                              0x00000002
+#ifndef NO_CS4612
+#define ACSTS_WKUP                              0x00000004
+#endif
+
+/*
+ *  The following defines are for the flags in the AC97 output slot valid
+ *  register.
+ */
+#define ACOSV_SLV3                              0x00000001
+#define ACOSV_SLV4                              0x00000002
+#define ACOSV_SLV5                              0x00000004
+#define ACOSV_SLV6                              0x00000008
+#define ACOSV_SLV7                              0x00000010
+#define ACOSV_SLV8                              0x00000020
+#define ACOSV_SLV9                              0x00000040
+#define ACOSV_SLV10                             0x00000080
+#define ACOSV_SLV11                             0x00000100
+#define ACOSV_SLV12                             0x00000200
+
+/*
+ *  The following defines are for the flags in the AC97 command address
+ *  register.
+ */
+#define ACCAD_CI_MASK                           0x0000007F
+#define ACCAD_CI_SHIFT                          0
+
+/*
+ *  The following defines are for the flags in the AC97 command data register.
+ */
+#define ACCDA_CD_MASK                           0x0000FFFF
+#define ACCDA_CD_SHIFT                          0
+
+/*
+ *  The following defines are for the flags in the AC97 input slot valid
+ *  register.
+ */
+#define ACISV_ISV3                              0x00000001
+#define ACISV_ISV4                              0x00000002
+#define ACISV_ISV5                              0x00000004
+#define ACISV_ISV6                              0x00000008
+#define ACISV_ISV7                              0x00000010
+#define ACISV_ISV8                              0x00000020
+#define ACISV_ISV9                              0x00000040
+#define ACISV_ISV10                             0x00000080
+#define ACISV_ISV11                             0x00000100
+#define ACISV_ISV12                             0x00000200
+
+/*
+ *  The following defines are for the flags in the AC97 status address
+ *  register.
+ */
+#define ACSAD_SI_MASK                           0x0000007F
+#define ACSAD_SI_SHIFT                          0
+
+/*
+ *  The following defines are for the flags in the AC97 status data register.
+ */
+#define ACSDA_SD_MASK                           0x0000FFFF
+#define ACSDA_SD_SHIFT                          0
+
+/*
+ *  The following defines are for the flags in the joystick poll/trigger
+ *  register.
+ */
+#define JSPT_CAX                                0x00000001
+#define JSPT_CAY                                0x00000002
+#define JSPT_CBX                                0x00000004
+#define JSPT_CBY                                0x00000008
+#define JSPT_BA1                                0x00000010
+#define JSPT_BA2                                0x00000020
+#define JSPT_BB1                                0x00000040
+#define JSPT_BB2                                0x00000080
+
+/*
+ *  The following defines are for the flags in the joystick control register.
+ */
+#define JSCTL_SP_MASK                           0x00000003
+#define JSCTL_SP_SLOW                           0x00000000
+#define JSCTL_SP_MEDIUM_SLOW                    0x00000001
+#define JSCTL_SP_MEDIUM_FAST                    0x00000002
+#define JSCTL_SP_FAST                           0x00000003
+#define JSCTL_ARE                               0x00000004
+
+/*
+ *  The following defines are for the flags in the joystick coordinate pair 1
+ *  readback register.
+ */
+#define JSC1_Y1V_MASK                           0x0000FFFF
+#define JSC1_X1V_MASK                           0xFFFF0000
+#define JSC1_Y1V_SHIFT                          0
+#define JSC1_X1V_SHIFT                          16
+
+/*
+ *  The following defines are for the flags in the joystick coordinate pair 2
+ *  readback register.
+ */
+#define JSC2_Y2V_MASK                           0x0000FFFF
+#define JSC2_X2V_MASK                           0xFFFF0000
+#define JSC2_Y2V_SHIFT                          0
+#define JSC2_X2V_SHIFT                          16
+
+/*
+ *  The following defines are for the flags in the MIDI control register.
+ */
+#define MIDCR_TXE                               0x00000001	/* Enable transmitting. */
+#define MIDCR_RXE                               0x00000002	/* Enable receiving. */
+#define MIDCR_RIE                               0x00000004	/* Interrupt upon tx ready. */
+#define MIDCR_TIE                               0x00000008	/* Interrupt upon rx ready. */
+#define MIDCR_MLB                               0x00000010	/* Enable midi loopback. */
+#define MIDCR_MRST                              0x00000020	/* Reset interface. */
+
+/*
+ *  The following defines are for the flags in the MIDI status register.
+ */
+#define MIDSR_TBF                               0x00000001	/* Tx FIFO is full. */
+#define MIDSR_RBE                               0x00000002	/* Rx FIFO is empty. */
+
+/*
+ *  The following defines are for the flags in the MIDI write port register.
+ */
+#define MIDWP_MWD_MASK                          0x000000FF
+#define MIDWP_MWD_SHIFT                         0
+
+/*
+ *  The following defines are for the flags in the MIDI read port register.
+ */
+#define MIDRP_MRD_MASK                          0x000000FF
+#define MIDRP_MRD_SHIFT                         0
+
+/*
+ *  The following defines are for the flags in the joystick GPIO register.
+ */
+#define JSIO_DAX                                0x00000001
+#define JSIO_DAY                                0x00000002
+#define JSIO_DBX                                0x00000004
+#define JSIO_DBY                                0x00000008
+#define JSIO_AXOE                               0x00000010
+#define JSIO_AYOE                               0x00000020
+#define JSIO_BXOE                               0x00000040
+#define JSIO_BYOE                               0x00000080
+
+/*
+ *  The following defines are for the flags in the master async/sync serial
+ *  port enable register.
+ */
+#ifndef NO_CS4612
+#define ASER_MASTER_ME                          0x00000001
+#endif
+
+/*
+ *  The following defines are for the flags in the configuration interface
+ *  register.
+ */
+#define CFGI_CLK                                0x00000001
+#define CFGI_DOUT                               0x00000002
+#define CFGI_DIN_EEN                            0x00000004
+#define CFGI_EELD                               0x00000008
+
+/*
+ *  The following defines are for the flags in the subsystem ID and vendor ID
+ *  register.
+ */
+#define SSVID_VID_MASK                          0x0000FFFF
+#define SSVID_SID_MASK                          0xFFFF0000
+#define SSVID_VID_SHIFT                         0
+#define SSVID_SID_SHIFT                         16
+
+/*
+ *  The following defines are for the flags in the GPIO pin interface register.
+ */
+#define GPIOR_VOLDN                             0x00000001
+#define GPIOR_VOLUP                             0x00000002
+#define GPIOR_SI2D                              0x00000004
+#define GPIOR_SI2OE                             0x00000008
+
+/*
+ *  The following defines are for the flags in the extended GPIO pin direction
+ *  register.
+ */
+#ifndef NO_CS4612
+#define EGPIODR_GPOE0                           0x00000001
+#define EGPIODR_GPOE1                           0x00000002
+#define EGPIODR_GPOE2                           0x00000004
+#define EGPIODR_GPOE3                           0x00000008
+#define EGPIODR_GPOE4                           0x00000010
+#define EGPIODR_GPOE5                           0x00000020
+#define EGPIODR_GPOE6                           0x00000040
+#define EGPIODR_GPOE7                           0x00000080
+#define EGPIODR_GPOE8                           0x00000100
+#endif
+
+/*
+ *  The following defines are for the flags in the extended GPIO pin polarity/
+ *  type register.
+ */
+#ifndef NO_CS4612
+#define EGPIOPTR_GPPT0                          0x00000001
+#define EGPIOPTR_GPPT1                          0x00000002
+#define EGPIOPTR_GPPT2                          0x00000004
+#define EGPIOPTR_GPPT3                          0x00000008
+#define EGPIOPTR_GPPT4                          0x00000010
+#define EGPIOPTR_GPPT5                          0x00000020
+#define EGPIOPTR_GPPT6                          0x00000040
+#define EGPIOPTR_GPPT7                          0x00000080
+#define EGPIOPTR_GPPT8                          0x00000100
+#endif
+
+/*
+ *  The following defines are for the flags in the extended GPIO pin sticky
+ *  register.
+ */
+#ifndef NO_CS4612
+#define EGPIOTR_GPS0                            0x00000001
+#define EGPIOTR_GPS1                            0x00000002
+#define EGPIOTR_GPS2                            0x00000004
+#define EGPIOTR_GPS3                            0x00000008
+#define EGPIOTR_GPS4                            0x00000010
+#define EGPIOTR_GPS5                            0x00000020
+#define EGPIOTR_GPS6                            0x00000040
+#define EGPIOTR_GPS7                            0x00000080
+#define EGPIOTR_GPS8                            0x00000100
+#endif
+
+/*
+ *  The following defines are for the flags in the extended GPIO ping wakeup
+ *  register.
+ */
+#ifndef NO_CS4612
+#define EGPIOWR_GPW0                            0x00000001
+#define EGPIOWR_GPW1                            0x00000002
+#define EGPIOWR_GPW2                            0x00000004
+#define EGPIOWR_GPW3                            0x00000008
+#define EGPIOWR_GPW4                            0x00000010
+#define EGPIOWR_GPW5                            0x00000020
+#define EGPIOWR_GPW6                            0x00000040
+#define EGPIOWR_GPW7                            0x00000080
+#define EGPIOWR_GPW8                            0x00000100
+#endif
+
+/*
+ *  The following defines are for the flags in the extended GPIO pin status
+ *  register.
+ */
+#ifndef NO_CS4612
+#define EGPIOSR_GPS0                            0x00000001
+#define EGPIOSR_GPS1                            0x00000002
+#define EGPIOSR_GPS2                            0x00000004
+#define EGPIOSR_GPS3                            0x00000008
+#define EGPIOSR_GPS4                            0x00000010
+#define EGPIOSR_GPS5                            0x00000020
+#define EGPIOSR_GPS6                            0x00000040
+#define EGPIOSR_GPS7                            0x00000080
+#define EGPIOSR_GPS8                            0x00000100
+#endif
+
+/*
+ *  The following defines are for the flags in the serial port 6 configuration
+ *  register.
+ */
+#ifndef NO_CS4612
+#define SERC6_ASDO2EN                           0x00000001
+#endif
+
+/*
+ *  The following defines are for the flags in the serial port 7 configuration
+ *  register.
+ */
+#ifndef NO_CS4612
+#define SERC7_ASDI2EN                           0x00000001
+#define SERC7_POSILB                            0x00000002
+#define SERC7_SIPOLB                            0x00000004
+#define SERC7_SOSILB                            0x00000008
+#define SERC7_SISOLB                            0x00000010
+#endif
+
+/*
+ *  The following defines are for the flags in the serial port AC link
+ *  configuration register.
+ */
+#ifndef NO_CS4612
+#define SERACC_CODEC_TYPE_MASK                  0x00000001
+#define SERACC_CODEC_TYPE_1_03                  0x00000000
+#define SERACC_CODEC_TYPE_2_0                   0x00000001
+#define SERACC_TWO_CODECS                       0x00000002
+#define SERACC_MDM                              0x00000004
+#define SERACC_HSP                              0x00000008
+#endif
+
+/*
+ *  The following defines are for the flags in the AC97 control register 2.
+ */
+#ifndef NO_CS4612
+#define ACCTL2_RSTN                             0x00000001
+#define ACCTL2_ESYN                             0x00000002
+#define ACCTL2_VFRM                             0x00000004
+#define ACCTL2_DCV                              0x00000008
+#define ACCTL2_CRW                              0x00000010
+#define ACCTL2_ASYN                             0x00000020
+#endif
+
+/*
+ *  The following defines are for the flags in the AC97 status register 2.
+ */
+#ifndef NO_CS4612
+#define ACSTS2_CRDY                             0x00000001
+#define ACSTS2_VSTS                             0x00000002
+#endif
+
+/*
+ *  The following defines are for the flags in the AC97 output slot valid
+ *  register 2.
+ */
+#ifndef NO_CS4612
+#define ACOSV2_SLV3                             0x00000001
+#define ACOSV2_SLV4                             0x00000002
+#define ACOSV2_SLV5                             0x00000004
+#define ACOSV2_SLV6                             0x00000008
+#define ACOSV2_SLV7                             0x00000010
+#define ACOSV2_SLV8                             0x00000020
+#define ACOSV2_SLV9                             0x00000040
+#define ACOSV2_SLV10                            0x00000080
+#define ACOSV2_SLV11                            0x00000100
+#define ACOSV2_SLV12                            0x00000200
+#endif
+
+/*
+ *  The following defines are for the flags in the AC97 command address
+ *  register 2.
+ */
+#ifndef NO_CS4612
+#define ACCAD2_CI_MASK                          0x0000007F
+#define ACCAD2_CI_SHIFT                         0
+#endif
+
+/*
+ *  The following defines are for the flags in the AC97 command data register
+ *  2.
+ */
+#ifndef NO_CS4612
+#define ACCDA2_CD_MASK                          0x0000FFFF
+#define ACCDA2_CD_SHIFT                         0
+#endif
+
+/*
+ *  The following defines are for the flags in the AC97 input slot valid
+ *  register 2.
+ */
+#ifndef NO_CS4612
+#define ACISV2_ISV3                             0x00000001
+#define ACISV2_ISV4                             0x00000002
+#define ACISV2_ISV5                             0x00000004
+#define ACISV2_ISV6                             0x00000008
+#define ACISV2_ISV7                             0x00000010
+#define ACISV2_ISV8                             0x00000020
+#define ACISV2_ISV9                             0x00000040
+#define ACISV2_ISV10                            0x00000080
+#define ACISV2_ISV11                            0x00000100
+#define ACISV2_ISV12                            0x00000200
+#endif
+
+/*
+ *  The following defines are for the flags in the AC97 status address
+ *  register 2.
+ */
+#ifndef NO_CS4612
+#define ACSAD2_SI_MASK                          0x0000007F
+#define ACSAD2_SI_SHIFT                         0
+#endif
+
+/*
+ *  The following defines are for the flags in the AC97 status data register 2.
+ */
+#ifndef NO_CS4612
+#define ACSDA2_SD_MASK                          0x0000FFFF
+#define ACSDA2_SD_SHIFT                         0
+#endif
+
+/*
+ *  The following defines are for the flags in the I/O trap address and control
+ *  registers (all 12).
+ */
+#ifndef NO_CS4612
+#define IOTAC_SA_MASK                           0x0000FFFF
+#define IOTAC_MSK_MASK                          0x000F0000
+#define IOTAC_IODC_MASK                         0x06000000
+#define IOTAC_IODC_16_BIT                       0x00000000
+#define IOTAC_IODC_10_BIT                       0x02000000
+#define IOTAC_IODC_12_BIT                       0x04000000
+#define IOTAC_WSPI                              0x08000000
+#define IOTAC_RSPI                              0x10000000
+#define IOTAC_WSE                               0x20000000
+#define IOTAC_WE                                0x40000000
+#define IOTAC_RE                                0x80000000
+#define IOTAC_SA_SHIFT                          0
+#define IOTAC_MSK_SHIFT                         16
+#endif
+
+/*
+ *  The following defines are for the flags in the I/O trap fast read registers
+ *  (all 8).
+ */
+#ifndef NO_CS4612
+#define IOTFR_D_MASK                            0x0000FFFF
+#define IOTFR_A_MASK                            0x000F0000
+#define IOTFR_R_MASK                            0x0F000000
+#define IOTFR_ALL                               0x40000000
+#define IOTFR_VL                                0x80000000
+#define IOTFR_D_SHIFT                           0
+#define IOTFR_A_SHIFT                           16
+#define IOTFR_R_SHIFT                           24
+#endif
+
+/*
+ *  The following defines are for the flags in the I/O trap FIFO register.
+ */
+#ifndef NO_CS4612
+#define IOTFIFO_BA_MASK                         0x00003FFF
+#define IOTFIFO_S_MASK                          0x00FF0000
+#define IOTFIFO_OF                              0x40000000
+#define IOTFIFO_SPIOF                           0x80000000
+#define IOTFIFO_BA_SHIFT                        0
+#define IOTFIFO_S_SHIFT                         16
+#endif
+
+/*
+ *  The following defines are for the flags in the I/O trap retry read data
+ *  register.
+ */
+#ifndef NO_CS4612
+#define IOTRRD_D_MASK                           0x0000FFFF
+#define IOTRRD_RDV                              0x80000000
+#define IOTRRD_D_SHIFT                          0
+#endif
+
+/*
+ *  The following defines are for the flags in the I/O trap FIFO pointer
+ *  register.
+ */
+#ifndef NO_CS4612
+#define IOTFP_CA_MASK                           0x00003FFF
+#define IOTFP_PA_MASK                           0x3FFF0000
+#define IOTFP_CA_SHIFT                          0
+#define IOTFP_PA_SHIFT                          16
+#endif
+
+/*
+ *  The following defines are for the flags in the I/O trap control register.
+ */
+#ifndef NO_CS4612
+#define IOTCR_ITD                               0x00000001
+#define IOTCR_HRV                               0x00000002
+#define IOTCR_SRV                               0x00000004
+#define IOTCR_DTI                               0x00000008
+#define IOTCR_DFI                               0x00000010
+#define IOTCR_DDP                               0x00000020
+#define IOTCR_JTE                               0x00000040
+#define IOTCR_PPE                               0x00000080
+#endif
+
+/*
+ *  The following defines are for the flags in the direct PCI data register.
+ */
+#ifndef NO_CS4612
+#define DPCID_D_MASK                            0xFFFFFFFF
+#define DPCID_D_SHIFT                           0
+#endif
+
+/*
+ *  The following defines are for the flags in the direct PCI address register.
+ */
+#ifndef NO_CS4612
+#define DPCIA_A_MASK                            0xFFFFFFFF
+#define DPCIA_A_SHIFT                           0
+#endif
+
+/*
+ *  The following defines are for the flags in the direct PCI command register.
+ */
+#ifndef NO_CS4612
+#define DPCIC_C_MASK                            0x0000000F
+#define DPCIC_C_IOREAD                          0x00000002
+#define DPCIC_C_IOWRITE                         0x00000003
+#define DPCIC_BE_MASK                           0x000000F0
+#endif
+
+/*
+ *  The following defines are for the flags in the PC/PCI request register.
+ */
+#ifndef NO_CS4612
+#define PCPCIR_RDC_MASK                         0x00000007
+#define PCPCIR_C_MASK                           0x00007000
+#define PCPCIR_REQ                              0x00008000
+#define PCPCIR_RDC_SHIFT                        0
+#define PCPCIR_C_SHIFT                          12
+#endif
+
+/*
+ *  The following defines are for the flags in the PC/PCI grant register.
+ */
+#ifndef NO_CS4612
+#define PCPCIG_GDC_MASK                         0x00000007
+#define PCPCIG_VL                               0x00008000
+#define PCPCIG_GDC_SHIFT                        0
+#endif
+
+/*
+ *  The following defines are for the flags in the PC/PCI master enable
+ *  register.
+ */
+#ifndef NO_CS4612
+#define PCPCIEN_EN                              0x00000001
+#endif
+
+/*
+ *  The following defines are for the flags in the extended PCI power
+ *  management control register.
+ */
+#ifndef NO_CS4612
+#define EPCIPMC_GWU                             0x00000001
+#define EPCIPMC_FSPC                            0x00000002
+#endif
+
+/*
+ *  The following defines are for the flags in the SP control register.
+ */
+#define SPCR_RUN                                0x00000001
+#define SPCR_STPFR                              0x00000002
+#define SPCR_RUNFR                              0x00000004
+#define SPCR_TICK                               0x00000008
+#define SPCR_DRQEN                              0x00000020
+#define SPCR_RSTSP                              0x00000040
+#define SPCR_OREN                               0x00000080
+#ifndef NO_CS4612
+#define SPCR_PCIINT                             0x00000100
+#define SPCR_OINTD                              0x00000200
+#define SPCR_CRE                                0x00008000
+#endif
+
+/*
+ *  The following defines are for the flags in the debug index register.
+ */
+#define DREG_REGID_MASK                         0x0000007F
+#define DREG_DEBUG                              0x00000080
+#define DREG_RGBK_MASK                          0x00000700
+#define DREG_TRAP                               0x00000800
+#if !defined(NO_CS4612)
+#if !defined(NO_CS4615)
+#define DREG_TRAPX                              0x00001000
+#endif
+#endif
+#define DREG_REGID_SHIFT                        0
+#define DREG_RGBK_SHIFT                         8
+#define DREG_RGBK_REGID_MASK                    0x0000077F
+#define DREG_REGID_R0                           0x00000010
+#define DREG_REGID_R1                           0x00000011
+#define DREG_REGID_R2                           0x00000012
+#define DREG_REGID_R3                           0x00000013
+#define DREG_REGID_R4                           0x00000014
+#define DREG_REGID_R5                           0x00000015
+#define DREG_REGID_R6                           0x00000016
+#define DREG_REGID_R7                           0x00000017
+#define DREG_REGID_R8                           0x00000018
+#define DREG_REGID_R9                           0x00000019
+#define DREG_REGID_RA                           0x0000001A
+#define DREG_REGID_RB                           0x0000001B
+#define DREG_REGID_RC                           0x0000001C
+#define DREG_REGID_RD                           0x0000001D
+#define DREG_REGID_RE                           0x0000001E
+#define DREG_REGID_RF                           0x0000001F
+#define DREG_REGID_RA_BUS_LOW                   0x00000020
+#define DREG_REGID_RA_BUS_HIGH                  0x00000038
+#define DREG_REGID_YBUS_LOW                     0x00000050
+#define DREG_REGID_YBUS_HIGH                    0x00000058
+#define DREG_REGID_TRAP_0                       0x00000100
+#define DREG_REGID_TRAP_1                       0x00000101
+#define DREG_REGID_TRAP_2                       0x00000102
+#define DREG_REGID_TRAP_3                       0x00000103
+#define DREG_REGID_TRAP_4                       0x00000104
+#define DREG_REGID_TRAP_5                       0x00000105
+#define DREG_REGID_TRAP_6                       0x00000106
+#define DREG_REGID_TRAP_7                       0x00000107
+#define DREG_REGID_INDIRECT_ADDRESS             0x0000010E
+#define DREG_REGID_TOP_OF_STACK                 0x0000010F
+#if !defined(NO_CS4612)
+#if !defined(NO_CS4615)
+#define DREG_REGID_TRAP_8                       0x00000110
+#define DREG_REGID_TRAP_9                       0x00000111
+#define DREG_REGID_TRAP_10                      0x00000112
+#define DREG_REGID_TRAP_11                      0x00000113
+#define DREG_REGID_TRAP_12                      0x00000114
+#define DREG_REGID_TRAP_13                      0x00000115
+#define DREG_REGID_TRAP_14                      0x00000116
+#define DREG_REGID_TRAP_15                      0x00000117
+#define DREG_REGID_TRAP_16                      0x00000118
+#define DREG_REGID_TRAP_17                      0x00000119
+#define DREG_REGID_TRAP_18                      0x0000011A
+#define DREG_REGID_TRAP_19                      0x0000011B
+#define DREG_REGID_TRAP_20                      0x0000011C
+#define DREG_REGID_TRAP_21                      0x0000011D
+#define DREG_REGID_TRAP_22                      0x0000011E
+#define DREG_REGID_TRAP_23                      0x0000011F
+#endif
+#endif
+#define DREG_REGID_RSA0_LOW                     0x00000200
+#define DREG_REGID_RSA0_HIGH                    0x00000201
+#define DREG_REGID_RSA1_LOW                     0x00000202
+#define DREG_REGID_RSA1_HIGH                    0x00000203
+#define DREG_REGID_RSA2                         0x00000204
+#define DREG_REGID_RSA3                         0x00000205
+#define DREG_REGID_RSI0_LOW                     0x00000206
+#define DREG_REGID_RSI0_HIGH                    0x00000207
+#define DREG_REGID_RSI1                         0x00000208
+#define DREG_REGID_RSI2                         0x00000209
+#define DREG_REGID_SAGUSTATUS                   0x0000020A
+#define DREG_REGID_RSCONFIG01_LOW               0x0000020B
+#define DREG_REGID_RSCONFIG01_HIGH              0x0000020C
+#define DREG_REGID_RSCONFIG23_LOW               0x0000020D
+#define DREG_REGID_RSCONFIG23_HIGH              0x0000020E
+#define DREG_REGID_RSDMA01E                     0x0000020F
+#define DREG_REGID_RSDMA23E                     0x00000210
+#define DREG_REGID_RSD0_LOW                     0x00000211
+#define DREG_REGID_RSD0_HIGH                    0x00000212
+#define DREG_REGID_RSD1_LOW                     0x00000213
+#define DREG_REGID_RSD1_HIGH                    0x00000214
+#define DREG_REGID_RSD2_LOW                     0x00000215
+#define DREG_REGID_RSD2_HIGH                    0x00000216
+#define DREG_REGID_RSD3_LOW                     0x00000217
+#define DREG_REGID_RSD3_HIGH                    0x00000218
+#define DREG_REGID_SRAR_HIGH                    0x0000021A
+#define DREG_REGID_SRAR_LOW                     0x0000021B
+#define DREG_REGID_DMA_STATE                    0x0000021C
+#define DREG_REGID_CURRENT_DMA_STREAM           0x0000021D
+#define DREG_REGID_NEXT_DMA_STREAM              0x0000021E
+#define DREG_REGID_CPU_STATUS                   0x00000300
+#define DREG_REGID_MAC_MODE                     0x00000301
+#define DREG_REGID_STACK_AND_REPEAT             0x00000302
+#define DREG_REGID_INDEX0                       0x00000304
+#define DREG_REGID_INDEX1                       0x00000305
+#define DREG_REGID_DMA_STATE_0_3                0x00000400
+#define DREG_REGID_DMA_STATE_4_7                0x00000404
+#define DREG_REGID_DMA_STATE_8_11               0x00000408
+#define DREG_REGID_DMA_STATE_12_15              0x0000040C
+#define DREG_REGID_DMA_STATE_16_19              0x00000410
+#define DREG_REGID_DMA_STATE_20_23              0x00000414
+#define DREG_REGID_DMA_STATE_24_27              0x00000418
+#define DREG_REGID_DMA_STATE_28_31              0x0000041C
+#define DREG_REGID_DMA_STATE_32_35              0x00000420
+#define DREG_REGID_DMA_STATE_36_39              0x00000424
+#define DREG_REGID_DMA_STATE_40_43              0x00000428
+#define DREG_REGID_DMA_STATE_44_47              0x0000042C
+#define DREG_REGID_DMA_STATE_48_51              0x00000430
+#define DREG_REGID_DMA_STATE_52_55              0x00000434
+#define DREG_REGID_DMA_STATE_56_59              0x00000438
+#define DREG_REGID_DMA_STATE_60_63              0x0000043C
+#define DREG_REGID_DMA_STATE_64_67              0x00000440
+#define DREG_REGID_DMA_STATE_68_71              0x00000444
+#define DREG_REGID_DMA_STATE_72_75              0x00000448
+#define DREG_REGID_DMA_STATE_76_79              0x0000044C
+#define DREG_REGID_DMA_STATE_80_83              0x00000450
+#define DREG_REGID_DMA_STATE_84_87              0x00000454
+#define DREG_REGID_DMA_STATE_88_91              0x00000458
+#define DREG_REGID_DMA_STATE_92_95              0x0000045C
+#define DREG_REGID_TRAP_SELECT                  0x00000500
+#define DREG_REGID_TRAP_WRITE_0                 0x00000500
+#define DREG_REGID_TRAP_WRITE_1                 0x00000501
+#define DREG_REGID_TRAP_WRITE_2                 0x00000502
+#define DREG_REGID_TRAP_WRITE_3                 0x00000503
+#define DREG_REGID_TRAP_WRITE_4                 0x00000504
+#define DREG_REGID_TRAP_WRITE_5                 0x00000505
+#define DREG_REGID_TRAP_WRITE_6                 0x00000506
+#define DREG_REGID_TRAP_WRITE_7                 0x00000507
+#if !defined(NO_CS4612)
+#if !defined(NO_CS4615)
+#define DREG_REGID_TRAP_WRITE_8                 0x00000510
+#define DREG_REGID_TRAP_WRITE_9                 0x00000511
+#define DREG_REGID_TRAP_WRITE_10                0x00000512
+#define DREG_REGID_TRAP_WRITE_11                0x00000513
+#define DREG_REGID_TRAP_WRITE_12                0x00000514
+#define DREG_REGID_TRAP_WRITE_13                0x00000515
+#define DREG_REGID_TRAP_WRITE_14                0x00000516
+#define DREG_REGID_TRAP_WRITE_15                0x00000517
+#define DREG_REGID_TRAP_WRITE_16                0x00000518
+#define DREG_REGID_TRAP_WRITE_17                0x00000519
+#define DREG_REGID_TRAP_WRITE_18                0x0000051A
+#define DREG_REGID_TRAP_WRITE_19                0x0000051B
+#define DREG_REGID_TRAP_WRITE_20                0x0000051C
+#define DREG_REGID_TRAP_WRITE_21                0x0000051D
+#define DREG_REGID_TRAP_WRITE_22                0x0000051E
+#define DREG_REGID_TRAP_WRITE_23                0x0000051F
+#endif
+#endif
+#define DREG_REGID_MAC0_ACC0_LOW                0x00000600
+#define DREG_REGID_MAC0_ACC1_LOW                0x00000601
+#define DREG_REGID_MAC0_ACC2_LOW                0x00000602
+#define DREG_REGID_MAC0_ACC3_LOW                0x00000603
+#define DREG_REGID_MAC1_ACC0_LOW                0x00000604
+#define DREG_REGID_MAC1_ACC1_LOW                0x00000605
+#define DREG_REGID_MAC1_ACC2_LOW                0x00000606
+#define DREG_REGID_MAC1_ACC3_LOW                0x00000607
+#define DREG_REGID_MAC0_ACC0_MID                0x00000608
+#define DREG_REGID_MAC0_ACC1_MID                0x00000609
+#define DREG_REGID_MAC0_ACC2_MID                0x0000060A
+#define DREG_REGID_MAC0_ACC3_MID                0x0000060B
+#define DREG_REGID_MAC1_ACC0_MID                0x0000060C
+#define DREG_REGID_MAC1_ACC1_MID                0x0000060D
+#define DREG_REGID_MAC1_ACC2_MID                0x0000060E
+#define DREG_REGID_MAC1_ACC3_MID                0x0000060F
+#define DREG_REGID_MAC0_ACC0_HIGH               0x00000610
+#define DREG_REGID_MAC0_ACC1_HIGH               0x00000611
+#define DREG_REGID_MAC0_ACC2_HIGH               0x00000612
+#define DREG_REGID_MAC0_ACC3_HIGH               0x00000613
+#define DREG_REGID_MAC1_ACC0_HIGH               0x00000614
+#define DREG_REGID_MAC1_ACC1_HIGH               0x00000615
+#define DREG_REGID_MAC1_ACC2_HIGH               0x00000616
+#define DREG_REGID_MAC1_ACC3_HIGH               0x00000617
+#define DREG_REGID_RSHOUT_LOW                   0x00000620
+#define DREG_REGID_RSHOUT_MID                   0x00000628
+#define DREG_REGID_RSHOUT_HIGH                  0x00000630
+
+/*
+ *  The following defines are for the flags in the DMA stream requestor write
+ */
+#define DSRWP_DSR_MASK                          0x0000000F
+#define DSRWP_DSR_BG_RQ                         0x00000001
+#define DSRWP_DSR_PRIORITY_MASK                 0x00000006
+#define DSRWP_DSR_PRIORITY_0                    0x00000000
+#define DSRWP_DSR_PRIORITY_1                    0x00000002
+#define DSRWP_DSR_PRIORITY_2                    0x00000004
+#define DSRWP_DSR_PRIORITY_3                    0x00000006
+#define DSRWP_DSR_RQ_PENDING                    0x00000008
+
+/*
+ *  The following defines are for the flags in the trap write port register.
+ */
+#define TWPR_TW_MASK                            0x0000FFFF
+#define TWPR_TW_SHIFT                           0
+
+/*
+ *  The following defines are for the flags in the stack pointer write
+ *  register.
+ */
+#define SPWR_STKP_MASK                          0x0000000F
+#define SPWR_STKP_SHIFT                         0
+
+/*
+ *  The following defines are for the flags in the SP interrupt register.
+ */
+#define SPIR_FRI                                0x00000001
+#define SPIR_DOI                                0x00000002
+#define SPIR_GPI2                               0x00000004
+#define SPIR_GPI3                               0x00000008
+#define SPIR_IP0                                0x00000010
+#define SPIR_IP1                                0x00000020
+#define SPIR_IP2                                0x00000040
+#define SPIR_IP3                                0x00000080
+
+/*
+ *  The following defines are for the flags in the functional group 1 register.
+ */
+#define FGR1_F1S_MASK                           0x0000FFFF
+#define FGR1_F1S_SHIFT                          0
+
+/*
+ *  The following defines are for the flags in the SP clock status register.
+ */
+#define SPCS_FRI                                0x00000001
+#define SPCS_DOI                                0x00000002
+#define SPCS_GPI2                               0x00000004
+#define SPCS_GPI3                               0x00000008
+#define SPCS_IP0                                0x00000010
+#define SPCS_IP1                                0x00000020
+#define SPCS_IP2                                0x00000040
+#define SPCS_IP3                                0x00000080
+#define SPCS_SPRUN                              0x00000100
+#define SPCS_SLEEP                              0x00000200
+#define SPCS_FG                                 0x00000400
+#define SPCS_ORUN                               0x00000800
+#define SPCS_IRQ                                0x00001000
+#define SPCS_FGN_MASK                           0x0000E000
+#define SPCS_FGN_SHIFT                          13
+
+/*
+ *  The following defines are for the flags in the SP DMA requestor status
+ *  register.
+ */
+#define SDSR_DCS_MASK                           0x000000FF
+#define SDSR_DCS_SHIFT                          0
+#define SDSR_DCS_NONE                           0x00000007
+
+/*
+ *  The following defines are for the flags in the frame timer register.
+ */
+#define FRMT_FTV_MASK                           0x0000FFFF
+#define FRMT_FTV_SHIFT                          0
+
+/*
+ *  The following defines are for the flags in the frame timer current count
+ *  register.
+ */
+#define FRCC_FCC_MASK                           0x0000FFFF
+#define FRCC_FCC_SHIFT                          0
+
+/*
+ *  The following defines are for the flags in the frame timer save count
+ *  register.
+ */
+#define FRSC_FCS_MASK                           0x0000FFFF
+#define FRSC_FCS_SHIFT                          0
+
+/*
+ *  The following define the various flags stored in the scatter/gather
+ *  descriptors.
+ */
+#define DMA_SG_NEXT_ENTRY_MASK                  0x00000FF8
+#define DMA_SG_SAMPLE_END_MASK                  0x0FFF0000
+#define DMA_SG_SAMPLE_END_FLAG                  0x10000000
+#define DMA_SG_LOOP_END_FLAG                    0x20000000
+#define DMA_SG_SIGNAL_END_FLAG                  0x40000000
+#define DMA_SG_SIGNAL_PAGE_FLAG                 0x80000000
+#define DMA_SG_NEXT_ENTRY_SHIFT                 3
+#define DMA_SG_SAMPLE_END_SHIFT                 16
+
+/*
+ *  The following define the offsets of the fields within the on-chip generic
+ *  DMA requestor.
+ */
+#define DMA_RQ_CONTROL1                         0x00000000
+#define DMA_RQ_CONTROL2                         0x00000004
+#define DMA_RQ_SOURCE_ADDR                      0x00000008
+#define DMA_RQ_DESTINATION_ADDR                 0x0000000C
+#define DMA_RQ_NEXT_PAGE_ADDR                   0x00000010
+#define DMA_RQ_NEXT_PAGE_SGDESC                 0x00000014
+#define DMA_RQ_LOOP_START_ADDR                  0x00000018
+#define DMA_RQ_POST_LOOP_ADDR                   0x0000001C
+#define DMA_RQ_PAGE_MAP_ADDR                    0x00000020
+
+/*
+ *  The following defines are for the flags in the first control word of the
+ *  on-chip generic DMA requestor.
+ */
+#define DMA_RQ_C1_COUNT_MASK                    0x000003FF
+#define DMA_RQ_C1_DESTINATION_SCATTER           0x00001000
+#define DMA_RQ_C1_SOURCE_GATHER                 0x00002000
+#define DMA_RQ_C1_DONE_FLAG                     0x00004000
+#define DMA_RQ_C1_OPTIMIZE_STATE                0x00008000
+#define DMA_RQ_C1_SAMPLE_END_STATE_MASK         0x00030000
+#define DMA_RQ_C1_FULL_PAGE                     0x00000000
+#define DMA_RQ_C1_BEFORE_SAMPLE_END             0x00010000
+#define DMA_RQ_C1_PAGE_MAP_ERROR                0x00020000
+#define DMA_RQ_C1_AT_SAMPLE_END                 0x00030000
+#define DMA_RQ_C1_LOOP_END_STATE_MASK           0x000C0000
+#define DMA_RQ_C1_NOT_LOOP_END                  0x00000000
+#define DMA_RQ_C1_BEFORE_LOOP_END               0x00040000
+#define DMA_RQ_C1_2PAGE_LOOP_BEGIN              0x00080000
+#define DMA_RQ_C1_LOOP_BEGIN                    0x000C0000
+#define DMA_RQ_C1_PAGE_MAP_MASK                 0x00300000
+#define DMA_RQ_C1_PM_NONE_PENDING               0x00000000
+#define DMA_RQ_C1_PM_NEXT_PENDING               0x00100000
+#define DMA_RQ_C1_PM_RESERVED                   0x00200000
+#define DMA_RQ_C1_PM_LOOP_NEXT_PENDING          0x00300000
+#define DMA_RQ_C1_WRITEBACK_DEST_FLAG           0x00400000
+#define DMA_RQ_C1_WRITEBACK_SRC_FLAG            0x00800000
+#define DMA_RQ_C1_DEST_SIZE_MASK                0x07000000
+#define DMA_RQ_C1_DEST_LINEAR                   0x00000000
+#define DMA_RQ_C1_DEST_MOD16                    0x01000000
+#define DMA_RQ_C1_DEST_MOD32                    0x02000000
+#define DMA_RQ_C1_DEST_MOD64                    0x03000000
+#define DMA_RQ_C1_DEST_MOD128                   0x04000000
+#define DMA_RQ_C1_DEST_MOD256                   0x05000000
+#define DMA_RQ_C1_DEST_MOD512                   0x06000000
+#define DMA_RQ_C1_DEST_MOD1024                  0x07000000
+#define DMA_RQ_C1_DEST_ON_HOST                  0x08000000
+#define DMA_RQ_C1_SOURCE_SIZE_MASK              0x70000000
+#define DMA_RQ_C1_SOURCE_LINEAR                 0x00000000
+#define DMA_RQ_C1_SOURCE_MOD16                  0x10000000
+#define DMA_RQ_C1_SOURCE_MOD32                  0x20000000
+#define DMA_RQ_C1_SOURCE_MOD64                  0x30000000
+#define DMA_RQ_C1_SOURCE_MOD128                 0x40000000
+#define DMA_RQ_C1_SOURCE_MOD256                 0x50000000
+#define DMA_RQ_C1_SOURCE_MOD512                 0x60000000
+#define DMA_RQ_C1_SOURCE_MOD1024                0x70000000
+#define DMA_RQ_C1_SOURCE_ON_HOST                0x80000000
+#define DMA_RQ_C1_COUNT_SHIFT                   0
+
+/*
+ *  The following defines are for the flags in the second control word of the
+ *  on-chip generic DMA requestor.
+ */
+#define DMA_RQ_C2_VIRTUAL_CHANNEL_MASK          0x0000003F
+#define DMA_RQ_C2_VIRTUAL_SIGNAL_MASK           0x00000300
+#define DMA_RQ_C2_NO_VIRTUAL_SIGNAL             0x00000000
+#define DMA_RQ_C2_SIGNAL_EVERY_DMA              0x00000100
+#define DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG        0x00000200
+#define DMA_RQ_C2_SIGNAL_DEST_PINGPONG          0x00000300
+#define DMA_RQ_C2_AUDIO_CONVERT_MASK            0x0000F000
+#define DMA_RQ_C2_AC_NONE                       0x00000000
+#define DMA_RQ_C2_AC_8_TO_16_BIT                0x00001000
+#define DMA_RQ_C2_AC_MONO_TO_STEREO             0x00002000
+#define DMA_RQ_C2_AC_ENDIAN_CONVERT             0x00004000
+#define DMA_RQ_C2_AC_SIGNED_CONVERT             0x00008000
+#define DMA_RQ_C2_LOOP_END_MASK                 0x0FFF0000
+#define DMA_RQ_C2_LOOP_MASK                     0x30000000
+#define DMA_RQ_C2_NO_LOOP                       0x00000000
+#define DMA_RQ_C2_ONE_PAGE_LOOP                 0x10000000
+#define DMA_RQ_C2_TWO_PAGE_LOOP                 0x20000000
+#define DMA_RQ_C2_MULTI_PAGE_LOOP               0x30000000
+#define DMA_RQ_C2_SIGNAL_LOOP_BACK              0x40000000
+#define DMA_RQ_C2_SIGNAL_POST_BEGIN_PAGE        0x80000000
+#define DMA_RQ_C2_VIRTUAL_CHANNEL_SHIFT         0
+#define DMA_RQ_C2_LOOP_END_SHIFT                16
+
+/*
+ *  The following defines are for the flags in the source and destination words
+ *  of the on-chip generic DMA requestor.
+ */
+#define DMA_RQ_SD_ADDRESS_MASK                  0x0000FFFF
+#define DMA_RQ_SD_MEMORY_ID_MASK                0x000F0000
+#define DMA_RQ_SD_SP_PARAM_ADDR                 0x00000000
+#define DMA_RQ_SD_SP_SAMPLE_ADDR                0x00010000
+#define DMA_RQ_SD_SP_PROGRAM_ADDR               0x00020000
+#define DMA_RQ_SD_SP_DEBUG_ADDR                 0x00030000
+#define DMA_RQ_SD_OMNIMEM_ADDR                  0x000E0000
+#define DMA_RQ_SD_END_FLAG                      0x40000000
+#define DMA_RQ_SD_ERROR_FLAG                    0x80000000
+#define DMA_RQ_SD_ADDRESS_SHIFT                 0
+
+/*
+ *  The following defines are for the flags in the page map address word of the
+ *  on-chip generic DMA requestor.
+ */
+#define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_MASK   0x00000FF8
+#define DMA_RQ_PMA_PAGE_TABLE_MASK              0xFFFFF000
+#define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_SHIFT  3
+#define DMA_RQ_PMA_PAGE_TABLE_SHIFT             12
+
+#define BA1_VARIDEC_BUF_1       0x000
+
+#define BA1_PDTC                0x0c0	/* BA1_PLAY_DMA_TRANSACTION_COUNT_REG */
+#define BA1_PFIE                0x0c4	/* BA1_PLAY_FORMAT_&_INTERRUPT_ENABLE_REG */
+#define BA1_PBA                 0x0c8	/* BA1_PLAY_BUFFER_ADDRESS */
+#define BA1_PVOL                0x0f8	/* BA1_PLAY_VOLUME_REG */
+#define BA1_PSRC                0x288	/* BA1_PLAY_SAMPLE_RATE_CORRECTION_REG */
+#define BA1_PCTL                0x2a4	/* BA1_PLAY_CONTROL_REG */
+#define BA1_PPI                 0x2b4	/* BA1_PLAY_PHASE_INCREMENT_REG */
+
+#define BA1_CCTL                0x064	/* BA1_CAPTURE_CONTROL_REG */
+#define BA1_CIE                 0x104	/* BA1_CAPTURE_INTERRUPT_ENABLE_REG */
+#define BA1_CBA                 0x10c	/* BA1_CAPTURE_BUFFER_ADDRESS */
+#define BA1_CSRC                0x2c8	/* BA1_CAPTURE_SAMPLE_RATE_CORRECTION_REG */
+#define BA1_CCI                 0x2d8	/* BA1_CAPTURE_COEFFICIENT_INCREMENT_REG */
+#define BA1_CD                  0x2e0	/* BA1_CAPTURE_DELAY_REG */
+#define BA1_CPI                 0x2f4	/* BA1_CAPTURE_PHASE_INCREMENT_REG */
+#define BA1_CVOL                0x2f8	/* BA1_CAPTURE_VOLUME_REG */
+
+#define BA1_CFG1                0x134	/* BA1_CAPTURE_FRAME_GROUP_1_REG */
+#define BA1_CFG2                0x138	/* BA1_CAPTURE_FRAME_GROUP_2_REG */
+#define BA1_CCST                0x13c	/* BA1_CAPTURE_CONSTANT_REG */
+#define BA1_CSPB                0x340	/* BA1_CAPTURE_SPB_ADDRESS */
+
+/*
+ *
+ */
+
+#define CS461X_MODE_OUTPUT	(1<<0)	/* MIDI UART - output */
+#define CS461X_MODE_INPUT	(1<<1)	/* MIDI UART - input */
+
+/****************************************************************************
+ *
+ * The following define the offsets of the AC97 shadow registers, which appear
+ * as a virtual extension to the base address register zero memory range.
+ *
+ ****************************************************************************/
+#define AC97_REG_OFFSET_MASK                    0x0000007EL
+#define AC97_CODEC_NUMBER_MASK                  0x00003000L
+
+#define BA0_AC97_RESET                          0x00001000L
+#define BA0_AC97_MASTER_VOLUME                  0x00001002L
+#define BA0_AC97_HEADPHONE_VOLUME               0x00001004L
+#define BA0_AC97_MASTER_VOLUME_MONO             0x00001006L
+#define BA0_AC97_MASTER_TONE                    0x00001008L
+#define BA0_AC97_PC_BEEP_VOLUME                 0x0000100AL
+#define BA0_AC97_PHONE_VOLUME                   0x0000100CL
+#define BA0_AC97_MIC_VOLUME                     0x0000100EL
+#define BA0_AC97_LINE_IN_VOLUME                 0x00001010L
+#define BA0_AC97_CD_VOLUME                      0x00001012L
+#define BA0_AC97_VIDEO_VOLUME                   0x00001014L
+#define BA0_AC97_AUX_VOLUME                     0x00001016L
+#define BA0_AC97_PCM_OUT_VOLUME                 0x00001018L
+#define BA0_AC97_RECORD_SELECT                  0x0000101AL
+#define BA0_AC97_RECORD_GAIN                    0x0000101CL
+#define BA0_AC97_RECORD_GAIN_MIC                0x0000101EL
+#define BA0_AC97_GENERAL_PURPOSE                0x00001020L
+#define BA0_AC97_3D_CONTROL                     0x00001022L
+#define BA0_AC97_MODEM_RATE                     0x00001024L
+#define BA0_AC97_POWERDOWN                      0x00001026L
+#define BA0_AC97_EXT_AUDIO_ID                   0x00001028L
+#define BA0_AC97_EXT_AUDIO_POWER                0x0000102AL
+#define BA0_AC97_PCM_FRONT_DAC_RATE             0x0000102CL
+#define BA0_AC97_PCM_SURR_DAC_RATE              0x0000102EL
+#define BA0_AC97_PCM_LFE_DAC_RATE               0x00001030L
+#define BA0_AC97_PCM_LR_ADC_RATE                0x00001032L
+#define BA0_AC97_MIC_ADC_RATE                   0x00001034L
+#define BA0_AC97_6CH_VOL_C_LFE                  0x00001036L
+#define BA0_AC97_6CH_VOL_SURROUND               0x00001038L
+#define BA0_AC97_RESERVED_3A                    0x0000103AL
+#define BA0_AC97_EXT_MODEM_ID                   0x0000103CL
+#define BA0_AC97_EXT_MODEM_POWER                0x0000103EL
+#define BA0_AC97_LINE1_CODEC_RATE               0x00001040L
+#define BA0_AC97_LINE2_CODEC_RATE               0x00001042L
+#define BA0_AC97_HANDSET_CODEC_RATE             0x00001044L
+#define BA0_AC97_LINE1_CODEC_LEVEL              0x00001046L
+#define BA0_AC97_LINE2_CODEC_LEVEL              0x00001048L
+#define BA0_AC97_HANDSET_CODEC_LEVEL            0x0000104AL
+#define BA0_AC97_GPIO_PIN_CONFIG                0x0000104CL
+#define BA0_AC97_GPIO_PIN_TYPE                  0x0000104EL
+#define BA0_AC97_GPIO_PIN_STICKY                0x00001050L
+#define BA0_AC97_GPIO_PIN_WAKEUP                0x00001052L
+#define BA0_AC97_GPIO_PIN_STATUS                0x00001054L
+#define BA0_AC97_MISC_MODEM_AFE_STAT            0x00001056L
+#define BA0_AC97_RESERVED_58                    0x00001058L
+#define BA0_AC97_CRYSTAL_REV_N_FAB_ID           0x0000105AL
+#define BA0_AC97_TEST_AND_MISC_CTRL             0x0000105CL
+#define BA0_AC97_AC_MODE                        0x0000105EL
+#define BA0_AC97_MISC_CRYSTAL_CONTROL           0x00001060L
+#define BA0_AC97_LINE1_HYPRID_CTRL              0x00001062L
+#define BA0_AC97_VENDOR_RESERVED_64             0x00001064L
+#define BA0_AC97_VENDOR_RESERVED_66             0x00001066L
+#define BA0_AC97_SPDIF_CONTROL                  0x00001068L
+#define BA0_AC97_VENDOR_RESERVED_6A             0x0000106AL
+#define BA0_AC97_VENDOR_RESERVED_6C             0x0000106CL
+#define BA0_AC97_VENDOR_RESERVED_6E             0x0000106EL
+#define BA0_AC97_VENDOR_RESERVED_70             0x00001070L
+#define BA0_AC97_VENDOR_RESERVED_72             0x00001072L
+#define BA0_AC97_VENDOR_RESERVED_74             0x00001074L
+#define BA0_AC97_CAL_ADDRESS                    0x00001076L
+#define BA0_AC97_CAL_DATA                       0x00001078L
+#define BA0_AC97_VENDOR_RESERVED_7A             0x0000107AL
+#define BA0_AC97_VENDOR_ID1                     0x0000107CL
+#define BA0_AC97_VENDOR_ID2                     0x0000107EL
diff --git a/kernel/drv/oss_cs461x/cs461x_dsp.h b/kernel/drv/oss_cs461x/cs461x_dsp.h
new file mode 100644
index 0000000..44c6da6
--- /dev/null
+++ b/kernel/drv/oss_cs461x/cs461x_dsp.h
@@ -0,0 +1,3474 @@
+/*
+ * Purpose: Firmware for cs461x/cs461x cards.
+ */
+/*
+ *
+ * This file is part of Open Sound System.
+ *
+ * Copyright (C) 4Front Technologies 1996-2008.
+ *
+ * This this source file is released under GPL v2 license (no other versions).
+ * See the COPYING file included in the main directory of this source
+ * distribution for the license terms and conditions.
+ *
+ */
+struct cs461x_firmware_struct cs461x_firmware = {
+  {{0x00000000, 0x00003000}, {0x00010000, 0x00003800},
+   {0x00020000, 0x00007000}},
+  {0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000163, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00200040, 0x00008010, 0x00000000,
+   0x00000000, 0x80000001, 0x00000001, 0x00060000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00900080, 0x00000173, 0x00000000,
+   0x00000000, 0x00000010, 0x00800000, 0x00900000,
+   0xf2c0000f, 0x00000200, 0x00000000, 0x00010600,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000163, 0x330300c2,
+   0x06000000, 0x00000000, 0x80008000, 0x80008000,
+   0x3fc0000f, 0x00000301, 0x00010400, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00b00000, 0x00d0806d, 0x330480c3,
+   0x04800000, 0x00000001, 0x00800001, 0x0000ffff,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x066a0130, 0x06350070, 0x0000929d, 0x929d929d,
+   0x00000000, 0x0000735a, 0x00000600, 0x00000000,
+   0x929d735a, 0x00000000, 0x00010000, 0x735a735a,
+   0xa431ac75, 0xa431ac75, 0xa431ac75, 0xa431ac75,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x000000f0, 0x0000804f, 0x000000c3,
+   0x05000000, 0x00a00010, 0x00000000, 0x80008000,
+   0x00000000, 0x00000000, 0x00000700, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000080, 0x00a00000, 0x0000809a, 0x000000c2,
+   0x07400000, 0x00000000, 0x80008000, 0xffffffff,
+   0x00c80028, 0x00005555, 0x00000000, 0x000107a0,
+   0x00c80028, 0x000000c2, 0x06800000, 0x00000000,
+   0x06e00080, 0x00300000, 0x000080bb, 0x000000c9,
+   0x07a00000, 0x04000000, 0x80008000, 0xffffffff,
+   0x00c80028, 0x00005555, 0x00000000, 0x00000780,
+   0x00c80028, 0x000000c5, 0xff800000, 0x00000000,
+   0x00640080, 0x00c00000, 0x00008197, 0x000000c9,
+   0x07800000, 0x04000000, 0x80008000, 0xffffffff,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x0000805e, 0x000000c1,
+   0x00000000, 0x00800000, 0x80008000, 0x80008000,
+   0x00020000, 0x0000ffff, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x07c00000, 0x00900000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x0000018e, 0x000000c2,
+   0x07c00000, 0x00000000, 0x80008000, 0xffffffff,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00e00100, 0x00000173, 0x00000000,
+   0x00000000, 0x00400010, 0x00800000, 0x00e00000,
+   0x00000000, 0x00000000, 0x08400000, 0x00900000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x01100000, 0x0000018e, 0x000000c2,
+   0x08400000, 0x00000000, 0x80008000, 0xffffffff,
+   0x007fff80, 0x00280058, 0x01300000, 0x00000000,
+   0x00000000, 0x2aab0000, 0x00000000, 0x00000000,
+   0x00000000, 0x01200000, 0x0000026c, 0x000000c2,
+   0x08c00000, 0x18000000, 0x80008000, 0x80008000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x0000805e, 0x000000c1,
+   0x00000000, 0x01000000, 0x80008000, 0x80008000,
+   0x00000000, 0x00000110, 0x00000000, 0x00000000,
+   0x00000000, 0x00000082, 0x09000000, 0x00000000,
+   0x00000000, 0x00000600, 0x013d0233, 0x20ff0040,
+   0x00000000, 0x0000804c, 0x000101d8, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
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+   0x00000000, 0x00000000, 0x00000000, 0x00010004,
+   0x00040730, 0x00001002, 0x000f619e, 0x00001003,
+   0x00001705, 0x00001400, 0x000a411e, 0x00001003,
+   0x00040730, 0x00001002, 0x000f619e, 0x00001003,
+   0x00009705, 0x00001400, 0x000a411e, 0x00001003,
+   0x00040730, 0x00001002, 0x000f619e, 0x00001003,
+   0x00011705, 0x00001400, 0x000a411e, 0x00001003,
+   0x00040730, 0x00001002, 0x000f619e, 0x00001003,
+   0x00019705, 0x00001400, 0x000a411e, 0x00001003,
+   0x00040730, 0x00001002, 0x000f619e, 0x00001003,
+   0x00021705, 0x00001400, 0x000a411e, 0x00001003,
+   0x00040730, 0x00001002, 0x000f619e, 0x00001003,
+   0x00029705, 0x00001400, 0x000a411e, 0x00001003,
+   0x00040730, 0x00001002, 0x000f619e, 0x00001003,
+   0x00031705, 0x00001400, 0x000a411e, 0x00001003,
+   0x00040730, 0x00001002, 0x000f619e, 0x00001003,
+   0x00039705, 0x00001400, 0x000a411e, 0x00001003,
+   0x000fe19e, 0x00001003, 0x0009c730, 0x00001003,
+   0x0008e19c, 0x00001003, 0x000083c1, 0x00093040,
+   0x00098730, 0x00001002, 0x000ee19e, 0x00001003,
+   0x00009705, 0x00001400, 0x000a211e, 0x00001003,
+   0x00098730, 0x00001002, 0x000ee19e, 0x00001003,
+   0x00011705, 0x00001400, 0x000a211e, 0x00001003,
+   0x00098730, 0x00001002, 0x000ee19e, 0x00001003,
+   0x00019705, 0x00001400, 0x000a211e, 0x00001003,
+   0x00098730, 0x00001002, 0x000ee19e, 0x00001003,
+   0x00021705, 0x00001400, 0x000a211e, 0x00001003,
+   0x00098730, 0x00001002, 0x000ee19e, 0x00001003,
+   0x00029705, 0x00001400, 0x000a211e, 0x00001003,
+   0x00098730, 0x00001002, 0x000ee19e, 0x00001003,
+   0x00031705, 0x00001400, 0x000a211e, 0x00001003,
+   0x00098730, 0x00001002, 0x000ee19e, 0x00001003,
+   0x00039705, 0x00001400, 0x000a211e, 0x00001003,
+   0x0000a730, 0x00001008, 0x000e2730, 0x00001002,
+   0x0000a731, 0x00001002, 0x0000a731, 0x00001002,
+   0x0000a731, 0x00001002, 0x0000a731, 0x00001002,
+   0x0000a731, 0x00001002, 0x0000a731, 0x00001002,
+   0x00000000, 0x00000000, 0x000f619c, 0x00001003,
+   0x0007f801, 0x000c0000, 0x00000037, 0x00001000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x000c0000, 0x00000000, 0x00000000,
+   0x0000373c, 0x00001000, 0x00000000, 0x00000000,
+   0x000ee19c, 0x00001003, 0x0007f801, 0x000c0000,
+   0x00000037, 0x00001000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x0000273c, 0x00001000,
+   0x00000033, 0x00001000, 0x000e679e, 0x00001003,
+   0x00007705, 0x00001400, 0x000ac71e, 0x00001003,
+   0x00087fc1, 0x000c3be0, 0x0007f801, 0x000c0000,
+   0x00000037, 0x00001000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x0000a730, 0x00001003,
+   0x00000033, 0x00001000, 0x0007f801, 0x000c0000,
+   0x00000037, 0x00001000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x000c0000,
+   0x00000032, 0x00001000, 0x0000273d, 0x00001000,
+   0x0004a730, 0x00001003, 0x00000f41, 0x00097140,
+   0x0000a841, 0x0009b240, 0x0000a0c1, 0x0009f040,
+   0x0001c641, 0x00093540, 0x0001cec1, 0x0009b5c0,
+   0x00000000, 0x00000000, 0x0001bf05, 0x0003fc40,
+   0x00002725, 0x000aa400, 0x00013705, 0x00093a00,
+   0x0000002e, 0x0009d6c0, 0x00038630, 0x00001004,
+   0x0004ef0a, 0x000eb785, 0x0003fc8a, 0x00000000,
+   0x00000000, 0x000c70e0, 0x0007d182, 0x0002c640,
+   0x00000630, 0x00001004, 0x000799b8, 0x0002c6c0,
+   0x00031705, 0x00092240, 0x00039f05, 0x000932c0,
+   0x0003520a, 0x00000000, 0x00040731, 0x0000100b,
+   0x00010705, 0x000b20c0, 0x00000000, 0x000eba44,
+   0x00032108, 0x000c60c4, 0x00065208, 0x000c2917,
+   0x000406b0, 0x00001007, 0x00012f05, 0x00036880,
+   0x0002818e, 0x000c0000, 0x0004410a, 0x00000000,
+   0x00040630, 0x00001007, 0x00029705, 0x000c0000,
+   0x00000000, 0x00000000, 0x00003fc1, 0x0003fc40,
+   0x000037c1, 0x00091b40, 0x00003fc1, 0x000911c0,
+   0x000037c1, 0x000957c0, 0x00003fc1, 0x000951c0,
+   0x000037c1, 0x00000000, 0x00003fc1, 0x000991c0,
+   0x000037c1, 0x00000000, 0x00003fc1, 0x0009d1c0,
+   0x000037c1, 0x00000000, 0x0001ccc1, 0x000915c0,
+   0x0001c441, 0x0009d800, 0x0009cdc1, 0x00091240,
+   0x0001c541, 0x00091d00, 0x0009cfc1, 0x00095240,
+   0x0001c741, 0x00095c80, 0x000e8ca9, 0x00099240,
+   0x000e85ad, 0x00095640, 0x00069ca9, 0x00099d80,
+   0x000e952d, 0x00099640, 0x000eaca9, 0x0009d6c0,
+   0x000ea5ad, 0x00091a40, 0x0006bca9, 0x0009de80,
+   0x000eb52d, 0x00095a40, 0x000ecca9, 0x00099ac0,
+   0x000ec5ad, 0x0009da40, 0x000edca9, 0x0009d300,
+   0x000a6e0a, 0x00001000, 0x000ed52d, 0x00091e40,
+   0x000eeca9, 0x00095ec0, 0x000ee5ad, 0x00099e40,
+   0x0006fca9, 0x00002500, 0x000fb208, 0x000c59a0,
+   0x000ef52d, 0x0009de40, 0x00068ca9, 0x000912c1,
+   0x000683ad, 0x00095241, 0x00020f05, 0x000991c1,
+   0x00000000, 0x00000000, 0x00086f88, 0x00001000,
+   0x0009cf81, 0x000b5340, 0x0009c701, 0x000b92c0,
+   0x0009de81, 0x000bd300, 0x0009d601, 0x000b1700,
+   0x0001fd81, 0x000b9d80, 0x0009f501, 0x000b57c0,
+   0x000a0f81, 0x000bd740, 0x00020701, 0x000b5c80,
+   0x000a1681, 0x000b97c0, 0x00021601, 0x00002500,
+   0x000a0701, 0x000b9b40, 0x000a0f81, 0x000b1bc0,
+   0x00021681, 0x00002d00, 0x00020f81, 0x000bd800,
+   0x000a0701, 0x000b5bc0, 0x00021601, 0x00003500,
+   0x000a0f81, 0x000b5f40, 0x000a0701, 0x000bdbc0,
+   0x00021681, 0x00003d00, 0x00020f81, 0x000b1d00,
+   0x000a0701, 0x000b1fc0, 0x00021601, 0x00020500,
+   0x00020f81, 0x000b1341, 0x000a0701, 0x000b9fc0,
+   0x00021681, 0x00020d00, 0x00020f81, 0x000bde80,
+   0x000a0701, 0x000bdfc0, 0x00021601, 0x00021500,
+   0x00020f81, 0x000b9341, 0x00020701, 0x000b53c1,
+   0x00021681, 0x00021d00, 0x000a0f81, 0x000d0380,
+   0x0000b601, 0x000b15c0, 0x00007b01, 0x00000000,
+   0x00007b81, 0x000bd1c0, 0x00007b01, 0x00000000,
+   0x00007b81, 0x000b91c0, 0x00007b01, 0x000b57c0,
+   0x00007b81, 0x000b51c0, 0x00007b01, 0x000b1b40,
+   0x00007b81, 0x000b11c0, 0x00087b01, 0x000c3dc0,
+   0x0007e488, 0x000d7e45, 0x00000000, 0x000d7a44,
+   0x0007e48a, 0x00000000, 0x00011f05, 0x00084080,
+   0x00000000, 0x00000000, 0x00001705, 0x000b3540,
+   0x00008a01, 0x000bf040, 0x00007081, 0x000bb5c0,
+   0x00055488, 0x00000000, 0x0000d482, 0x0003fc40,
+   0x0003fc88, 0x00000000, 0x0001e401, 0x000b3a00,
+   0x0001ec81, 0x000bd6c0, 0x0004ef08, 0x000eb784,
+   0x000c86b0, 0x00001007, 0x00008281, 0x000bb240,
+   0x0000b801, 0x000b7140, 0x00007888, 0x00000000,
+   0x0000073c, 0x00001000, 0x0007f188, 0x000c0000,
+   0x00000000, 0x00000000, 0x00055288, 0x000c555c,
+   0x0005528a, 0x000c0000, 0x0009fa88, 0x000c5d00,
+   0x0000fa88, 0x00000000, 0x00000032, 0x00001000,
+   0x0000073d, 0x00001000, 0x0007f188, 0x000c0000,
+   0x00000000, 0x00000000, 0x0008c01c, 0x00001003,
+   0x00002705, 0x00001008, 0x0008b201, 0x000c1392,
+   0x0000ba01, 0x00000000, 0x00008731, 0x00001400,
+   0x0004c108, 0x000fe0c4, 0x00057488, 0x00000000,
+   0x000a6388, 0x00001001, 0x0008b334, 0x000bc141,
+   0x0003020e, 0x00000000, 0x000886b0, 0x00001008,
+   0x00003625, 0x000c5dfa, 0x000a638a, 0x00001001,
+   0x0008020e, 0x00001002, 0x0008a6b0, 0x00001008,
+   0x0007f301, 0x00000000, 0x00000000, 0x00000000,
+   0x00002725, 0x000a8c40, 0x000000ae, 0x00000000,
+   0x000d8630, 0x00001008, 0x00000000, 0x000c74e0,
+   0x0007d182, 0x0002d640, 0x000a8630, 0x00001008,
+   0x000799b8, 0x0002d6c0, 0x0000748a, 0x000c3ec5,
+   0x0007420a, 0x000c0000, 0x00062208, 0x000c4117,
+   0x00070630, 0x00001009, 0x00000000, 0x000c0000,
+   0x0001022e, 0x00000000, 0x0003a630, 0x00001009,
+   0x00000000, 0x000c0000, 0x00000036, 0x00001000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x0002a730, 0x00001008, 0x0007f801, 0x000c0000,
+   0x00000037, 0x00001000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x0002a730, 0x00001008,
+   0x00000033, 0x00001000, 0x0002a705, 0x00001008,
+   0x00007a01, 0x000c0000, 0x000e6288, 0x000d550a,
+   0x0006428a, 0x00000000, 0x00060730, 0x0000100a,
+   0x00000000, 0x000c0000, 0x00000000, 0x00000000,
+   0x0007aab0, 0x00034880, 0x00078fb0, 0x0000100b,
+   0x00057488, 0x00000000, 0x00033b94, 0x00081140,
+   0x000183ae, 0x00000000, 0x000786b0, 0x0000100b,
+   0x00022f05, 0x000c3545, 0x0000eb8a, 0x00000000,
+   0x00042731, 0x00001003, 0x0007aab0, 0x00034880,
+   0x00048fb0, 0x0000100a, 0x00057488, 0x00000000,
+   0x00033b94, 0x00081140, 0x000183ae, 0x00000000,
+   0x000806b0, 0x0000100b, 0x00022f05, 0x00000000,
+   0x00007401, 0x00091140, 0x00048f05, 0x000951c0,
+   0x00042731, 0x00001003, 0x0000473d, 0x00001000,
+   0x000f19b0, 0x000bbc47, 0x00080000, 0x000bffc7,
+   0x000fe19e, 0x00001003, 0x00000000, 0x00000000,
+   0x0008e19c, 0x00001003, 0x000083c1, 0x00093040,
+   0x00000f41, 0x00097140, 0x0000a841, 0x0009b240,
+   0x0000a0c1, 0x0009f040, 0x0001c641, 0x00093540,
+   0x0001cec1, 0x0009b5c0, 0x00000000, 0x000fdc44,
+   0x00055208, 0x00000000, 0x00010705, 0x000a2880,
+   0x0000a23a, 0x00093a00, 0x0003fc8a, 0x000df6c5,
+   0x0004ef0a, 0x000c0000, 0x00012f05, 0x00036880,
+   0x00065308, 0x000c2997, 0x000d86b0, 0x0000100a,
+   0x0004410a, 0x000d40c7, 0x00000000, 0x00000000,
+   0x00080730, 0x00001004, 0x00056f0a, 0x000ea105,
+   0x00000000, 0x00000000, 0x0000473d, 0x00001000,
+   0x000f19b0, 0x000bbc47, 0x00080000, 0x000bffc7,
+   0x0000273d, 0x00001000, 0x00000000, 0x000eba44,
+   0x00048f05, 0x0000f440, 0x00007401, 0x0000f7c0,
+   0x00000734, 0x00001000, 0x00010705, 0x000a6880,
+   0x00006a88, 0x000c75c4, 0x00000000, 0x000e5084,
+   0x00000000, 0x000eba44, 0x00087401, 0x000e4782,
+   0x00000734, 0x00001000, 0x00010705, 0x000a6880,
+   0x00006a88, 0x000c75c4, 0x0007c108, 0x000c0000,
+   0x0007e721, 0x000bed40, 0x00005f25, 0x000badc0,
+   0x0003ba97, 0x000beb80, 0x00065590, 0x000b2e00,
+   0x00033217, 0x00003ec0, 0x00065590, 0x000b8e40,
+   0x0003ed80, 0x000491c0, 0x00073fb0, 0x00074c80,
+   0x000283a0, 0x0000100c, 0x000ee388, 0x00042970,
+   0x00008301, 0x00021ef2, 0x000b8f14, 0x0000000f,
+   0x000c4d8d, 0x0000001b, 0x000d6dc2, 0x000e06c6,
+   0x000032ac, 0x000c3916, 0x0004edc2, 0x00074c80,
+   0x00078898, 0x00001000, 0x00038894, 0x00000032,
+   0x000c4d8d, 0x00092e1b, 0x000d6dc2, 0x000e06c6,
+   0x0004edc2, 0x000c1956, 0x0000722c, 0x00034a00,
+   0x00041705, 0x0009ed40, 0x00058730, 0x00001400,
+   0x000d7488, 0x000c3a00, 0x00048f05, 0x00000000,
+   0x0007bfb0, 0x000bc240, 0x00000c2e, 0x000c6084,
+   0x000e8630, 0x0000100c, 0x00006408, 0x000efb84,
+   0x00016008, 0x00000000, 0x0001c088, 0x000c0000,
+   0x000fc908, 0x000e3392, 0x0005f488, 0x000efb84,
+   0x0001d402, 0x000b2e00, 0x0003d418, 0x00001000,
+   0x0008d574, 0x000c4293, 0x00065625, 0x000ea30e,
+   0x00096c01, 0x000c6f92, 0x0001a58a, 0x000c6085,
+   0x00002f43, 0x00000000, 0x000103a0, 0x0000100d,
+   0x0005e608, 0x000c0000, 0x00000000, 0x00000000,
+   0x000ca108, 0x000dcca1, 0x00003bac, 0x000c3205,
+   0x00073843, 0x00000000, 0x00040730, 0x0000100d,
+   0x0001600a, 0x000c0000, 0x00057488, 0x00000000,
+   0x00000000, 0x000e5084, 0x00000000, 0x000eba44,
+   0x00087401, 0x000e4782, 0x00000734, 0x00001000,
+   0x00010705, 0x000a6880, 0x00006a88, 0x000c75c4,
+   0x0006a108, 0x000cf2c4, 0x0004f4c0, 0x00000000,
+   0x000fa418, 0x0000101f, 0x0005d402, 0x0001c500,
+   0x000e8630, 0x0000100d, 0x00004418, 0x00001380,
+   0x000e243d, 0x000d394a, 0x00049705, 0x00000000,
+   0x0007d530, 0x000b4240, 0x000d80f2, 0x0000100d,
+   0x00009134, 0x000ca20a, 0x00004c90, 0x00001000,
+   0x0005d705, 0x00000000, 0x00004f25, 0x00098240,
+   0x00004725, 0x00000000, 0x0000e48a, 0x00000000,
+   0x00027295, 0x0009c2c0, 0x0003df25, 0x00000000,
+   0x000e0030, 0x0000100e, 0x0005f718, 0x000ac600,
+   0x0007cf30, 0x000c2a01, 0x0007a630, 0x0000100e,
+   0x000484a0, 0x0000100e, 0x00029314, 0x000bcb80,
+   0x0003cf25, 0x000b0e00, 0x0004f5c0, 0x00000000,
+   0x00049118, 0x000d888a, 0x0007dd02, 0x000c6efa,
+   0x00000000, 0x00000000, 0x0004f5c0, 0x00069c80,
+   0x0000d402, 0x00000000, 0x000e0630, 0x0000100e,
+   0x00079130, 0x00000000, 0x00049118, 0x00090e00,
+   0x0006c10a, 0x00000000, 0x00000000, 0x000c0000,
+   0x0007cf30, 0x00030580, 0x00005725, 0x00000000,
+   0x000d04a0, 0x0000100e, 0x00029314, 0x000b4780,
+   0x0003cf25, 0x000b8600, 0x00000000, 0x00000000,
+   0x00000000, 0x000c0000, 0x00000000, 0x00042c80,
+   0x0001dec1, 0x000e488c, 0x00031114, 0x00000000,
+   0x0004f5c2, 0x00000000, 0x0003640a, 0x00000000,
+   0x00000000, 0x000e5084, 0x00000000, 0x000eb844,
+   0x00007001, 0x00000000, 0x00000734, 0x00001000,
+   0x00010705, 0x000a6880, 0x00006a88, 0x000c75c4,
+   0x00036488, 0x00000000, 0x0000c403, 0x00001000,
+   0x000fa6b1, 0x00001010, 0x00014403, 0x00001000,
+   0x0006a6b1, 0x00001011, 0x0006a108, 0x000cf2c4,
+   0x0004f4c0, 0x000d5384, 0x0007e48a, 0x00000000,
+   0x00067718, 0x00001000, 0x0007a418, 0x00001000,
+   0x0007221a, 0x00000000, 0x0005d402, 0x00014500,
+   0x000d8630, 0x0000100f, 0x00004418, 0x00001780,
+   0x000e243d, 0x000d394a, 0x00049705, 0x00000000,
+   0x0007d530, 0x000b4240, 0x000cc0f2, 0x0000100f,
+   0x00014414, 0x00000000, 0x00004c90, 0x00001000,
+   0x0005d705, 0x00000000, 0x00004f25, 0x00098240,
+   0x00004725, 0x00000000, 0x0000e48a, 0x00000000,
+   0x00027295, 0x0009c2c0, 0x0007df25, 0x00000000,
+   0x000cc030, 0x00001010, 0x0005f718, 0x000fe798,
+   0x00029314, 0x000bcb80, 0x00000930, 0x000b0e00,
+   0x0004f5c0, 0x000de204, 0x000a84a0, 0x00001010,
+   0x0007cf25, 0x000e3560, 0x00049118, 0x00000000,
+   0x00049118, 0x000d888a, 0x0007dd02, 0x000c6efa,
+   0x0000c434, 0x00030040, 0x000fda82, 0x000c2312,
+   0x000fdc0e, 0x00001001, 0x00083402, 0x000c2b92,
+   0x000906b0, 0x00001010, 0x00075a82, 0x00000000,
+   0x0000d625, 0x000b0940, 0x0000840e, 0x00001002,
+   0x0000aabc, 0x000c511e, 0x00098730, 0x00001010,
+   0x0000aaf4, 0x000e910a, 0x0004628a, 0x00000000,
+   0x00006aca, 0x00000000, 0x00000930, 0x00000000,
+   0x0004f5c0, 0x00069c80, 0x00046ac0, 0x00000000,
+   0x0003c40a, 0x000fc898, 0x00049118, 0x00090e00,
+   0x0006c10a, 0x00000000, 0x00000000, 0x000e5084,
+   0x00000000, 0x000eb844, 0x00007001, 0x00000000,
+   0x00000734, 0x00001000, 0x00010705, 0x000a6880,
+   0x00006a88, 0x000c75c4, 0x00048f05, 0x00001402,
+   0x00051705, 0x00001402, 0x00046dc0, 0x000feac1,
+   0x0005a6b0, 0x00001011, 0x00085f25, 0x000c2b92,
+   0x000475c2, 0x00000000, 0x00005f05, 0x00001400,
+   0x00046dc2, 0x00000000, 0x00000f05, 0x00001402,
+   0x0003a508, 0x00000000, 0x00005f05, 0x00001400,
+   0x00046dc2, 0x00000000, 0x00004438, 0x000d9205,
+   0x0000273d, 0x00001000, 0x00048f05, 0x00001402,
+   0x00085f25, 0x000c2b92, 0x00046dc2, 0x000c621c,
+   0x0003240a, 0x000c0000, 0x00046dc0, 0x00000000,
+   0x0000273d, 0x00001000, 0x00066488, 0x00000000,
+   0x0000c403, 0x00001000, 0x0009a6b1, 0x00001012,
+   0x00014403, 0x00001000, 0x0003a6b1, 0x00001013,
+   0x0006a108, 0x00000000, 0x00023c18, 0x00001000,
+   0x0004f4c0, 0x000c3245, 0x0000a418, 0x00001000,
+   0x0003a20a, 0x00000000, 0x00004418, 0x00001380,
+   0x000e243d, 0x000d394a, 0x000c9705, 0x000def92,
+   0x0006c030, 0x00001012, 0x0005f718, 0x000fe798,
+   0x000504a0, 0x00001012, 0x00029314, 0x000b4780,
+   0x0003cf25, 0x000b8600, 0x00005725, 0x00000000,
+   0x00000000, 0x000c05d7, 0x00000000, 0x00042c80,
+   0x0001dec1, 0x000e488c, 0x000b1114, 0x000c2f12,
+   0x0004f5c2, 0x00000000, 0x0004a918, 0x00098600,
+   0x0006c28a, 0x00000000, 0x00000000, 0x000e5084,
+   0x00000000, 0x000eb844, 0x00007001, 0x00000000,
+   0x00000734, 0x00001000, 0x00010705, 0x000a6880,
+   0x00006a88, 0x000c75c4, 0x00069705, 0x00001402,
+   0x00038f05, 0x00001400, 0x000475c0, 0x000feac1,
+   0x000fa6b0, 0x00001012, 0x00046dc0, 0x00000000,
+   0x00085518, 0x0000100f, 0x00045534, 0x000f9285,
+   0x00068f05, 0x00001402, 0x00046588, 0x000feedd,
+   0x00046dc2, 0x00000000, 0x00070f05, 0x00001402,
+   0x0005e588, 0x000e36e1, 0x00000000, 0x000c5084,
+   0x00002f25, 0x000f2a84, 0x00005518, 0x000017fc,
+   0x0006550a, 0x00000000, 0x0000551a, 0x00001002,
+   0x0003450a, 0x000f6145, 0x0000473d, 0x00001000,
+   0x00004438, 0x000f1205, 0x00005f25, 0x00000000,
+   0x00068f05, 0x00001402, 0x00005725, 0x000e36e1,
+   0x0000c438, 0x000f1205, 0x0000273d, 0x00001000,
+   0x0002a880, 0x000b4e40, 0x00042214, 0x000e5548,
+   0x000542bf, 0x00000000, 0x00000000, 0x000481c0,
+   0x00000000, 0x00000000, 0x00000000, 0x00000030,
+   0x0000072d, 0x000fbf8a, 0x00077f94, 0x000ea7df,
+   0x0002ac95, 0x000d3145, 0x00002731, 0x00001400,
+   0x00006288, 0x000c71c4, 0x00014108, 0x000e6044,
+   0x00035408, 0x00000000, 0x00025418, 0x000a0ec0,
+   0x0001443d, 0x000ca21e, 0x00046595, 0x000d730c,
+   0x0006538e, 0x00000000, 0x0000c630, 0x00001014,
+   0x000e7b0e, 0x000df782, 0x0001c6b0, 0x00001014,
+   0x00036f05, 0x000c0000, 0x00043695, 0x000d598c,
+   0x0005331a, 0x000f2185, 0x00000000, 0x00000000,
+   0x000007ae, 0x000bdb00, 0x00040630, 0x00001400,
+   0x0005e708, 0x000c0000, 0x0007ef30, 0x000b1c00,
+   0x000806a0, 0x00001014, 0x00066408, 0x000c0000,
+   0x00000000, 0x00000000, 0x00021843, 0x00000000,
+   0x00000cac, 0x00062c00, 0x00001dac, 0x00063400,
+   0x00002cac, 0x0006cc80, 0x000db943, 0x000e5ca1,
+   0x00000000, 0x00000000, 0x0006680a, 0x000f3205,
+   0x00042730, 0x00001400, 0x00014108, 0x000f2204,
+   0x00025418, 0x000a2ec0, 0x00015dbd, 0x00038100,
+   0x00015dbc, 0x00000000, 0x0005e415, 0x00034880,
+   0x0001258a, 0x000d730c, 0x0006538e, 0x000baa40,
+   0x00008630, 0x00001015, 0x00067b0e, 0x000ac380,
+   0x0003ef05, 0x00000000, 0x0000f734, 0x0001c300,
+   0x000586b0, 0x00001400, 0x000b6f05, 0x000c3a00,
+   0x00048f05, 0x00000000, 0x0005b695, 0x0008c380,
+   0x0002058e, 0x00000000, 0x000500b0, 0x00001400,
+   0x0002b318, 0x000e998d, 0x0006430a, 0x00000000,
+   0x00000000, 0x000ef384, 0x00004725, 0x000c0000,
+   0x00000000, 0x000f3204, 0x00004f25, 0x000c0000,
+   0x00080000, 0x000e5ca1, 0x000cb943, 0x000e5ca1,
+   0x0004b943, 0x00000000, 0x00040730, 0x00001400,
+   0x000cb943, 0x000e5ca1, 0x0004b943, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
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+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
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+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000,
+   0x00000000, 0x00000000, 0x00000000, 0x00000000}
+};
diff --git a/kernel/drv/oss_cs461x/oss_cs461x.c b/kernel/drv/oss_cs461x/oss_cs461x.c
new file mode 100644
index 0000000..e024fc6
--- /dev/null
+++ b/kernel/drv/oss_cs461x/oss_cs461x.c
@@ -0,0 +1,1931 @@
+/*
+ * Purpose: Driver for Crystal cs461x and cs461x PCI audio controllers
+ */
+/*
+ *
+ * This file is part of Open Sound System.
+ *
+ * Copyright (C) 4Front Technologies 1996-2008.
+ *
+ * This this source file is released under GPL v2 license (no other versions).
+ * See the COPYING file included in the main directory of this source
+ * distribution for the license terms and conditions.
+ *
+ */
+
+#include "oss_cs461x_cfg.h"
+#include "midi_core.h"
+#include "ac97.h"
+#include "oss_pci.h"
+#include "cs461x.h"
+
+extern int cs461x_clkrun_fix;
+
+#define CRYSTAL_VENDOR_ID	0x1013
+#define CRYSTAL_CS4610_ID	0x6001
+#define CRYSTAL_CS461x_ID	0x6003
+#define CRYSTAL_CS4615_ID	0x6004
+
+#define USE_SG
+
+#define WRITEB(a,d) devc->bRegister0[a] = d
+#define READB(a) devc->bRegister0[a]
+#define WRITEW(a,d) devc->wRegister0[a>>1] = d
+#define READW(a) devc->wRegister0[a>>1]
+
+#define READ0L(a) (devc->dwRegister0[a>>2])
+#define WRITE0L(a, d) (devc->dwRegister0[a>>2] = d)
+#define READ1L(a) (devc->dwRegister1[a>>2])
+#define WRITE1L(a,d) (devc->dwRegister1[a>>2] = d)
+
+#define READ1L(a) (devc->dwRegister1[a>>2])
+
+#ifdef OSS_BIG_ENDIAN
+static unsigned int
+ymf_swap (unsigned int x)
+{
+  return ((x & 0x000000ff) << 24) |
+    ((x & 0x0000ff00) << 8) |
+    ((x & 0x00ff0000) >> 8) | ((x & 0xff000000) >> 24);
+}
+
+#define LSWAP(x) ymf_swap(x)
+#else
+#define LSWAP(x) 	x
+#endif
+
+#define MAX_PORTC 2
+
+typedef struct cs461x_portc
+{
+  int speed, bits, channels;
+  int open_mode;
+  int audio_enabled;
+  int trigger_bits;
+  int audiodev;
+}
+cs461x_portc;
+
+typedef struct cs461x_devc
+{
+  oss_device_t *osdev;
+  char *chip_name;
+  unsigned short subsysid;
+
+  oss_native_word bar0addr, bar1addr;
+  unsigned int *bar0virt, *bar1virt;
+  volatile unsigned int *dwRegister0, *dwRegister1;
+  volatile unsigned short *wRegister0, *wRegister1;
+  volatile unsigned char *bRegister0, *bRegister1;
+  int irq;
+  int dual_codec;
+  unsigned int *play_sgbuf;
+  unsigned int play_sgbuf_phys;
+  oss_dma_handle_t play_sgbuf_dma_handle;
+
+  /* Mutex */
+  oss_mutex_t mutex;
+  oss_mutex_t low_mutex;
+
+  /* MIDI */
+  int midi_opened;
+  int midi_dev;
+  oss_midi_inputbyte_t midi_input_intr;
+
+  /* Mixer parameters */
+  ac97_devc ac97devc, ac97devc2;
+  int mixer_dev, mixer2_dev;
+
+  /* Audio parameters */
+  cs461x_portc portc[MAX_PORTC];
+  int open_mode;
+  oss_native_word PCTL;		/*Play Control Register */
+  oss_native_word CCTL;		/*Record Control Register */
+  int processor_started;
+}
+cs461x_devc;
+
+#define MAX_CS461x 6
+
+static int ac97_write (void *devc, int addr, int data);
+static int ac97_read (void *devc, int addr);
+
+static void
+PokeBA0 (cs461x_devc * devc, unsigned int offset, unsigned int value)
+{
+  WRITE0L (offset, value);
+}
+
+static unsigned int
+PeekBA0 (cs461x_devc * devc, unsigned int offset)
+{
+  unsigned int value;
+
+  value = READ0L (offset);
+  return (value);
+
+}
+
+static int
+ac97_read (void *devc_, int offset)
+{
+  cs461x_devc *devc = devc_;
+  int count;
+  unsigned int status, value;
+  oss_native_word flags;
+
+  MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags);
+  /*
+   * Make sure that there is not data sitting around from a previous
+   * uncompleted access. ACSDA = Status Data Register = 47Ch
+   */
+  status = PeekBA0 (devc, BA0_ACSDA);
+  /* Get the actual AC97 register from the offset */
+  PokeBA0 (devc, BA0_ACCAD, offset - BA0_AC97_RESET);
+  PokeBA0 (devc, BA0_ACCDA, 0);
+  PokeBA0 (devc, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM |
+	   ACCTL_ESYN | ACCTL_RSTN);
+
+  /* Wait for the read to occur. */
+  for (count = 0; count < 10; count++)
+    {
+      /* First, we want to wait for a short time. */
+      oss_udelay (100);
+      /*
+       * Now, check to see if the read has completed.
+       * ACCTL = 460h, DCV should be reset by now and 460h = 17h
+       */
+      status = PeekBA0 (devc, BA0_ACCTL);
+      if (!(status & ACCTL_DCV))
+	{
+	  break;
+	}
+    }
+
+  /* Make sure the read completed. */
+  if (status & ACCTL_DCV)
+    {
+      cmn_err (CE_WARN, "AC97 Read Timedout\n");
+      MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags);
+      return (-1);
+    }
+
+  /* Wait for the valid status bit to go active. */
+
+  for (count = 0; count < 10; count++)
+    {
+      /*
+       * Read the AC97 status register.
+       * ACSTS = Status Register = 464h
+       */
+      status = PeekBA0 (devc, BA0_ACSTS);
+      /*
+       * See if we have valid status.
+       * VSTS - Valid Status
+       */
+      if (status & ACSTS_VSTS)
+	break;
+
+      /*
+       * Wait for a short while.
+       */
+      oss_udelay (100);
+    }
+  /* Make sure we got valid status. */
+  if (!(status & ACSTS_VSTS))
+    {
+      cmn_err (CE_WARN, "AC97 Read Timedout(2)\n");
+      MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags);
+      return (-1);
+    }
+
+  /*
+   * Read the data returned from the AC97 register.
+   * ACSDA = Status Data Register = 474h
+   */
+  value = PeekBA0 (devc, BA0_ACSDA);
+  MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags);
+  return (value);
+}
+
+static int
+ac97_write (void *devc_, int offset, int data)
+{
+  cs461x_devc *devc = devc_;
+  int count;
+  unsigned int status = 0;
+  oss_native_word flags;
+
+  MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags);
+  PokeBA0 (devc, BA0_ACCAD, offset);
+  PokeBA0 (devc, BA0_ACCDA, data);
+  PokeBA0 (devc, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
+  for (count = 0; count < 10; count++)
+    {
+      /* First, we want to wait for a short time. */
+      oss_udelay (100);
+      /* Now, check to see if the write has completed. */
+      /* ACCTL = 460h, DCV should be reset by now and 460h = 07h */
+      status = PeekBA0 (devc, BA0_ACCTL);
+      if (!(status & ACCTL_DCV))
+	break;
+    }
+
+  /* write didn't completed. */
+  if (status & ACCTL_DCV)
+    {
+      cmn_err (CE_WARN, "AC97 Write timeout\n");
+      MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags);
+      return (-1);
+    }
+  MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags);
+  return 0;
+}
+
+static int
+ac97_read2 (void *devc_, int offset)
+{
+  cs461x_devc *devc = devc_;
+  int count;
+  unsigned int status, value;
+  oss_native_word flags;
+
+  MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags);
+  /*
+   * Make sure that there is not data sitting around from a previous
+   * uncompleted access. ACSDA = Status Data Register = 47Ch
+   */
+  status = PeekBA0 (devc, BA0_ACSDA2);
+
+  /* Get the actual AC97 register from the offset */
+  PokeBA0 (devc, BA0_ACCAD, offset);
+  PokeBA0 (devc, BA0_ACCDA, 0);
+  PokeBA0 (devc, BA0_ACCTL,
+	   ACCTL_DCV | ACCTL_TC | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
+	   ACCTL_RSTN);
+
+
+  /* Wait for the read to occur. */
+  for (count = 0; count < 10; count++)
+    {
+      /* First, we want to wait for a short time. */
+      oss_udelay (1000);
+      /*
+       * Now, check to see if the read has completed.
+       * ACCTL = 460h, DCV should be reset by now and 460h = 17h
+       */
+      status = PeekBA0 (devc, BA0_ACCTL);
+      if (!(status & ACCTL_DCV))
+	break;
+    }
+
+  /* Make sure the read completed. */
+  if (PeekBA0 (devc, BA0_ACCTL) & ACCTL_DCV)
+    {
+      cmn_err (CE_WARN, "Secondary AC97 Read Timedout\n");
+      MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags);
+      return (-1);
+    }
+
+  /* Wait for the valid status bit to go active. */
+
+  for (count = 0; count < 10; count++)
+    {
+      /*
+       * Read the AC97 status register.
+       * ACSTS = Status Register = 464h
+       */
+      status = PeekBA0 (devc, BA0_ACSTS2);
+      /*
+       * See if we have valid status.
+       * VSTS - Valid Status
+       */
+      if (status & ACSTS_VSTS)
+	break;
+
+      /*
+       * Wait for a short while.
+       */
+      oss_udelay (1000);
+    }
+  /* Make sure we got valid status */
+  if (!(status & ACSTS_VSTS))
+    {
+      cmn_err (CE_WARN, "Secondary AC97 Read Timedout(2)\n");
+      MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags);
+      return (-1);
+    }
+
+  /*
+   * Read the data returned from the AC97 register.
+   * ACSDA = Status Data Register = 474h
+   */
+  value = PeekBA0 (devc, BA0_ACSDA2);
+  MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags);
+  return (value);
+}
+
+static int
+ac97_write2 (void *devc_, int offset, int data)
+{
+  cs461x_devc *devc = devc_;
+  int count;
+  unsigned int status = 0;
+  oss_native_word flags;
+
+  MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags);
+  PokeBA0 (devc, BA0_ACCAD, offset);
+  PokeBA0 (devc, BA0_ACCDA, data);
+  PokeBA0 (devc, BA0_ACCTL,
+	   ACCTL_DCV | ACCTL_TC | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
+  for (count = 0; count < 10; count++)
+    {
+      /* First, we want to wait for a short time. */
+      oss_udelay (1000);
+      /* Now, check to see if the write has completed. */
+      /* ACCTL = 460h, DCV should be reset by now and 460h = 07h */
+      status = PeekBA0 (devc, BA0_ACCTL);
+      if (!(status & ACCTL_DCV))
+	break;
+    }
+
+  /* write didn't completed. */
+  if (status & ACCTL_DCV)
+    {
+      cmn_err (CE_WARN, "Secondary AC97 Write timeout\n");
+      MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags);
+      return (-1);
+    }
+  MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags);
+  return 0;
+}
+
+/*  
+ * this is 3*1024 for parameter, 3.5*1024 for sample and 2*3.5*1024 
+ * for code since each instruction is 40 bits and takes two dwords
+ */
+#define INKY_BA1_DWORD_SIZE (13 * 1024 + 512)
+/* this is parameter, sample, and code */
+#define INKY_MEMORY_COUNT 3
+struct cs461x_firmware_struct
+{
+  struct
+  {
+    unsigned int ulDestAddr;
+    unsigned int ulSourceSize;
+  }
+  MemoryStat[INKY_MEMORY_COUNT];
+  unsigned int BA1Array[INKY_BA1_DWORD_SIZE];
+};
+#include "cs461x_dsp.h"
+
+static void
+DoTransfer (cs461x_devc * devc, unsigned int *fpulSrc,
+	    unsigned int ulByteDestOffset, unsigned int ulByteLength)
+{
+  int dwByteCounter;
+
+  if (ulByteDestOffset & 0x3)
+    {
+      cmn_err (CE_WARN, "invalid DMA address\n");
+      return;
+    }
+
+  for (dwByteCounter = 0; dwByteCounter < ulByteLength; dwByteCounter += 4)
+    {
+      WRITE1L ((ulByteDestOffset + dwByteCounter),
+	       fpulSrc[dwByteCounter / 4]);
+    }
+}
+
+static void
+install_ucode (cs461x_devc * devc)
+{
+  unsigned int i, count;
+
+  count = 0;
+  for (i = 0; i < INKY_MEMORY_COUNT; i++)
+    {
+
+      DoTransfer (devc, (unsigned int *) (cs461x_firmware.BA1Array + count),
+		  cs461x_firmware.MemoryStat[i].ulDestAddr,
+		  cs461x_firmware.MemoryStat[i].ulSourceSize);
+      count += cs461x_firmware.MemoryStat[i].ulSourceSize / 4;
+    }
+}
+
+void
+clear_serial_fifo (cs461x_devc * devc)
+{
+  unsigned int ulIdx, ulLoop;
+  unsigned int ulStatus = 0;
+  unsigned int ulCLKCR1;
+
+
+  ulCLKCR1 = PeekBA0 (devc, BA0_CLKCR1);
+
+  if (!(ulCLKCR1 & CLKCR1_SWCE))
+    {
+      PokeBA0 (devc, BA0_CLKCR1, ulCLKCR1 | CLKCR1_SWCE);
+    }
+  PokeBA0 (devc, BA0_SERBWP, 0);
+
+  for (ulIdx = 0; ulIdx < 256; ulIdx++)
+    {
+      /*
+       * Make sure the previous FIFO write operation has completed.
+       */
+      for (ulLoop = 0; ulLoop < 5; ulLoop++)
+	{
+	  oss_udelay (100);
+	  ulStatus = PeekBA0 (devc, BA0_SERBST);
+	  if (!(ulStatus & SERBST_WBSY))
+	    {
+	      break;
+	    }
+	}
+
+      if (ulStatus & SERBST_WBSY)
+	{
+	  if (!(ulCLKCR1 & CLKCR1_SWCE))
+	    {
+	      PokeBA0 (devc, BA0_CLKCR1, ulCLKCR1);
+	    }
+	}
+
+      /* Write the serial port FIFO index. */
+
+      PokeBA0 (devc, BA0_SERBAD, ulIdx);
+
+      /*
+       * Tell the serial port to load the new value into the FIFO location.
+       */
+      PokeBA0 (devc, BA0_SERBCM, SERBCM_WRC);
+    }
+
+  /*
+   * Now, if we powered up the devices, then power them back down again.
+   * This is kinda ugly, but should never happen.
+   */
+  if (!(ulCLKCR1 & CLKCR1_SWCE))
+    {
+      PokeBA0 (devc, BA0_CLKCR1, ulCLKCR1);
+    }
+
+}
+
+static int
+cs461x_reset_processor (cs461x_devc * devc)
+{
+  unsigned int ulIdx;
+
+  /* Write the reset bit of the SP control register. */
+  WRITE1L (BA1_SPCR, SPCR_RSTSP);
+  WRITE1L (BA1_SPCR, SPCR_DRQEN);
+
+  /* Clear the trap registers. */
+  for (ulIdx = 0; ulIdx < 8; ulIdx++)
+    {
+      WRITE1L (BA1_DREG, DREG_REGID_TRAP_SELECT + ulIdx);
+      WRITE1L (BA1_TWPR, 0xFFFF);
+    }
+
+  WRITE1L (BA1_DREG, 0);
+  WRITE1L (BA1_FRMT, 0xadf);
+  return (0);
+}
+
+static int
+cs461x_start_processor (cs461x_devc * devc)
+{
+
+  unsigned int ulCount;
+  int ulTemp = 0;
+
+  /* reset the processor first */
+  cs461x_reset_processor (devc);
+
+  /* reload the ucode */
+  install_ucode (devc);
+
+  /* Set the frame timer to reflect the number of cycles per frame. */
+  WRITE1L (BA1_FRMT, 0xADF);
+
+  /*
+   * Turn on the run, run at frame, and DMA enable bits in the local copy of
+   * the SP control register.
+   */
+  WRITE1L (BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
+
+  /*
+   * Wait until the run at frame bit resets itself in the SP control
+   * register.
+   */
+  for (ulCount = 0; ulCount < 25; ulCount++)
+    {
+      /* Wait a little bit, so we don't issue PCI reads too frequently. */
+      oss_udelay (100);
+
+      /* Fetch the current value of the SP status register. */
+      ulTemp = READ1L (BA1_SPCR);
+
+      /* If the run at frame bit has reset, then stop waiting. */
+      if (!(ulTemp & SPCR_RUNFR))
+	break;
+    }
+  /* If the run at frame bit never reset, then return an error. */
+  if (ulTemp & SPCR_RUNFR)
+    {
+      cmn_err (CE_WARN, "Start(): SPCR_RUNFR never reset.\n");
+    }
+  devc->processor_started = 1;
+  return 0;
+}
+
+static int
+cs461xintr (oss_device_t * osdev)
+{
+  cs461x_devc *devc = (cs461x_devc *) osdev->devc;
+  cs461x_portc *portc;
+  unsigned int status;
+  int i;
+  unsigned int uart_stat;
+  int serviced = 0;
+  oss_native_word flags;
+
+  MUTEX_ENTER_IRQDISABLE (devc->mutex, flags);
+
+/* Read the Interrupt Status Register */
+  status = PeekBA0 (devc, BA0_HISR);
+
+/*
+ * This is the MIDI read interrupt service. First check to see
+ * if the MIDI interrupt flag is set in the HISR register. Next
+ * read the MIDI status register. See if Receive Buffer Empty 
+ * is empty (0=FIFO Not empty, 1=FIFO is empty
+ */
+  if ((devc->midi_opened & OPEN_READ) && (status & HISR_MIDI))
+    {
+      uart_stat = PeekBA0 (devc, BA0_MIDSR);
+/*
+ * read one byte of MIDI data and hand it off the the sequencer module
+ * to decode this. Keep checking to see if the data is available. Stop
+ * when no more data is there in the FIFO.
+ */
+      while (!(uart_stat & MIDSR_RBE))
+	{
+	  unsigned char d;
+	  d = PeekBA0 (devc, BA0_MIDRP);
+
+	  if (devc->midi_opened & OPEN_READ && devc->midi_input_intr)
+	    devc->midi_input_intr (devc->midi_dev, d);
+	  uart_stat = PeekBA0 (devc, BA0_MIDSR);
+	}
+    }
+
+/* Audio interrupt handling */
+  if (status & 0x3)
+    {
+      for (i = 0; i < MAX_PORTC; i++)
+	{
+	  portc = &devc->portc[i];
+	  if (status & 0x1)
+	    if (portc->trigger_bits & PCM_ENABLE_OUTPUT)
+	      {
+		dmap_t *dmap = audio_engines[portc->audiodev]->dmap_out;
+		int ptr, n;
+
+		ptr = READ1L (BA1_PBA) - dmap->dmabuf_phys;
+		ptr = ptr / dmap->fragment_size;
+		if (ptr < 0 || ptr >= dmap->nfrags)
+		  ptr = 0;
+		n = 0;
+		while (dmap_get_qhead (dmap) != ptr && n++ < dmap->nfrags)
+		  oss_audio_outputintr (portc->audiodev, 0);
+	      }
+
+	  if (status & 0x2)
+	    if (portc->trigger_bits & PCM_ENABLE_INPUT)
+	      {
+
+		dmap_t *dmap = audio_engines[portc->audiodev]->dmap_in;
+		int ptr, n;
+
+		ptr = READ1L (BA1_CBA) - dmap->dmabuf_phys;
+		ptr = ptr / (dmap->fragment_size);
+
+		if (ptr < 0 || ptr >= dmap->nfrags)
+		  ptr = 0;
+		n = 0;
+		while (dmap_get_qtail (dmap) != ptr && n++ < dmap->nfrags)
+		  oss_audio_inputintr (portc->audiodev, 0);
+	      }
+	}
+    }
+
+  serviced = 1;
+  PokeBA0 (devc, BA0_HICR, 0x03);
+
+  MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+
+  return serviced;
+}
+
+static int
+cs461x_audio_set_rate (int dev, int arg)
+{
+  cs461x_portc *portc = audio_engines[dev]->portc;
+
+  if (arg == 0)
+    return portc->speed;
+
+  if (audio_engines[dev]->flags & ADEV_FIXEDRATE)
+    {
+      audio_engines[dev]->fixed_rate = 48000;
+      arg = 48000;
+    }
+  else
+    audio_engines[dev]->fixed_rate = 0;
+
+  if (arg > 48000)
+    arg = 48000;
+  if (arg < 5000)
+    arg = 5000;
+  portc->speed = arg;
+  return portc->speed;
+}
+
+static short
+cs461x_audio_set_channels (int dev, short arg)
+{
+  cs461x_portc *portc = audio_engines[dev]->portc;
+
+  if (audio_engines[dev]->flags & ADEV_STEREOONLY)
+    arg = 2;
+
+  if ((arg != 1) && (arg != 2))
+    return portc->channels;
+  portc->channels = arg;
+
+  return portc->channels;
+}
+
+static unsigned int
+cs461x_audio_set_format (int dev, unsigned int arg)
+{
+  cs461x_portc *portc = audio_engines[dev]->portc;
+
+  if (arg == 0)
+    return portc->bits;
+
+  if (audio_engines[dev]->flags & ADEV_16BITONLY)
+    arg = 16;
+
+  if (!(arg & (AFMT_U8 | AFMT_S16_LE)))
+    return portc->bits;
+  portc->bits = arg;
+
+  return portc->bits;
+}
+
+/*ARGSUSED*/
+static int
+cs461x_audio_ioctl (int dev, unsigned int cmd, ioctl_arg arg)
+{
+  return OSS_EINVAL;
+}
+
+static void cs461x_audio_trigger (int dev, int state);
+
+static void
+cs461x_audio_reset (int dev)
+{
+  cs461x_audio_trigger (dev, 0);
+}
+
+static void
+cs461x_audio_reset_input (int dev)
+{
+  cs461x_portc *portc = audio_engines[dev]->portc;
+  cs461x_audio_trigger (dev, portc->trigger_bits & ~PCM_ENABLE_INPUT);
+}
+
+static void
+cs461x_audio_reset_output (int dev)
+{
+  cs461x_portc *portc = audio_engines[dev]->portc;
+  cs461x_audio_trigger (dev, portc->trigger_bits & ~PCM_ENABLE_OUTPUT);
+}
+
+/*ARGSUSED*/
+static int
+cs461x_audio_open (int dev, int mode, int open_flags)
+{
+  cs461x_portc *portc = audio_engines[dev]->portc;
+  cs461x_devc *devc = audio_engines[dev]->devc;
+  oss_native_word flags;
+
+  MUTEX_ENTER_IRQDISABLE (devc->mutex, flags);
+  if (portc->open_mode)
+    {
+      MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+      return OSS_EBUSY;
+    }
+
+  if (devc->open_mode & mode)
+    {
+      MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+      return OSS_EBUSY;
+    }
+
+  devc->open_mode |= mode;
+
+  portc->open_mode = mode;
+  portc->audio_enabled &= ~mode;
+#if 0
+  if (mode & OPEN_READ)
+    {
+      dmapin->buffsize = 4096;
+      audio_engines[dev]->fixed_rate = 48000;
+      audio_engines[dev]->min_rate = 48000;
+      audio_engines[dev]->max_rate = 48000;
+      audio_engines[dev]->flags |=
+	ADEV_FIXEDRATE | ADEV_16BITONLY | ADEV_STEREOONLY;
+    }
+  if (mode & OPEN_WRITE)
+    {
+      audio_engines[dev]->min_rate = 5000;
+      audio_engines[dev]->max_rate = 48000;
+      audio_engines[dev]->flags &=
+	~(ADEV_FIXEDRATE | ADEV_16BITONLY | ADEV_STEREOONLY);
+      audio_engines[dev]->fixed_rate = 0;
+    }
+#endif
+  MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+  return 0;
+}
+
+static void
+cs461x_audio_close (int dev, int mode)
+{
+  cs461x_portc *portc = audio_engines[dev]->portc;
+  cs461x_devc *devc = audio_engines[dev]->devc;
+
+  cs461x_audio_reset (dev);
+  portc->audio_enabled &= ~mode;
+  devc->open_mode &= ~mode;
+  portc->open_mode = 0;
+}
+
+/*ARGSUSED*/
+static void
+cs461x_audio_output_block (int dev, oss_native_word buf, int count,
+			   int fragsize, int intrflag)
+{
+  cs461x_portc *portc = audio_engines[dev]->portc;
+
+  portc->audio_enabled |= PCM_ENABLE_OUTPUT;
+  portc->trigger_bits &= ~PCM_ENABLE_OUTPUT;
+}
+
+/*ARGSUSED*/
+static void
+cs461x_audio_start_input (int dev, oss_native_word buf, int count,
+			  int fragsize, int intrflag)
+{
+  cs461x_portc *portc = audio_engines[dev]->portc;
+
+  portc->audio_enabled |= PCM_ENABLE_INPUT;
+  portc->trigger_bits &= ~PCM_ENABLE_INPUT;
+}
+
+static void
+cs461x_audio_trigger (int dev, int state)
+{
+  oss_native_word flags, tmp;
+  cs461x_devc *devc = audio_engines[dev]->devc;
+  cs461x_portc *portc = audio_engines[dev]->portc;
+
+  MUTEX_ENTER_IRQDISABLE (devc->mutex, flags);
+  if (portc->open_mode & OPEN_WRITE)
+    {
+      if (state & PCM_ENABLE_OUTPUT)
+	{
+	  if ((portc->audio_enabled & PCM_ENABLE_OUTPUT) &&
+	      !(portc->trigger_bits & PCM_ENABLE_OUTPUT))
+	    {
+	      tmp = READ1L (BA1_PCTL);
+	      tmp &= 0xFFFF;
+	      tmp |= devc->PCTL;
+	      WRITE1L (BA1_PCTL, tmp);
+	      portc->trigger_bits |= PCM_ENABLE_OUTPUT;
+	    }
+	}
+      else
+	{
+	  if ((portc->audio_enabled & PCM_ENABLE_OUTPUT) &&
+	      (portc->trigger_bits & PCM_ENABLE_OUTPUT))
+	    {
+	      portc->trigger_bits &= ~PCM_ENABLE_OUTPUT;
+	      portc->audio_enabled &= ~PCM_ENABLE_OUTPUT;
+	      tmp = READ1L (BA1_PCTL);
+	      tmp &= 0xFFFF;
+	      WRITE1L (BA1_PCTL, tmp);
+	    }
+	}
+    }
+
+  if (portc->open_mode & OPEN_READ)
+    {
+      if (state & PCM_ENABLE_INPUT)
+	{
+	  if ((portc->audio_enabled & PCM_ENABLE_INPUT) &&
+	      !(portc->trigger_bits & PCM_ENABLE_INPUT))
+	    {
+	      tmp = READ1L (BA1_CCTL);
+	      tmp &= 0xFFFF0000;
+	      tmp |= devc->CCTL;
+	      WRITE1L (BA1_CCTL, tmp);
+	      portc->trigger_bits |= PCM_ENABLE_INPUT;
+	    }
+	}
+      else
+	{
+	  if ((portc->audio_enabled & PCM_ENABLE_INPUT) &&
+	      (portc->trigger_bits & PCM_ENABLE_INPUT))
+	    {
+	      portc->trigger_bits &= ~PCM_ENABLE_INPUT;
+	      portc->audio_enabled &= ~PCM_ENABLE_INPUT;
+	      tmp = READ1L (BA1_CCTL);
+	      tmp &= 0xFFFF0000;
+	      WRITE1L (BA1_CCTL, tmp);
+	    }
+	}
+    }
+  MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+}
+
+static int
+cs461x_play_rate (cs461x_devc * devc, unsigned int ulInRate)
+{
+/*define GOF_PER_SEC 200*/
+  unsigned int ulTemp1, ulTemp2;
+  unsigned int ulPhiIncr;
+  unsigned int ulCorrectionPerGOF, ulCorrectionPerSec;
+  unsigned int ulOutRate = 48000;
+
+  ulTemp1 = ulInRate << 16;
+  ulPhiIncr = ulTemp1 / ulOutRate;
+  ulTemp1 -= ulPhiIncr * ulOutRate;
+  ulTemp1 <<= 10;
+  ulPhiIncr <<= 10;
+  ulTemp2 = ulTemp1 / ulOutRate;
+  ulPhiIncr += ulTemp2;
+  ulTemp1 -= ulTemp2 * ulOutRate;
+  ulCorrectionPerGOF = ulTemp1 / 200;
+  ulTemp1 -= ulCorrectionPerGOF * 200;
+  ulCorrectionPerSec = ulTemp1;
+
+  /* Fill in the SampleRateConverter control block. */
+  WRITE1L (BA1_PSRC, ((ulCorrectionPerSec << 16) & 0xFFFF0000) |
+	   (ulCorrectionPerGOF & 0xFFFF));
+  WRITE1L (BA1_PPI, ulPhiIncr);
+  return 0;
+}
+
+static int
+cs461x_record_rate (cs461x_devc * devc, int ulOutRate)
+{
+  unsigned int ulPhiIncr, ulCoeffIncr, ulTemp1, ulTemp2;
+  unsigned int ulCorrectionPerGOF, ulCorrectionPerSec, ulInitialDelay;
+  unsigned int ulInRate = 48000;
+
+  /*
+   * We can only decimate by up to a factor of 1/9th the hardware rate.
+   * Return an error if an attempt is made to stray outside that limit.
+   */
+  if ((ulOutRate * 9) < ulInRate)
+    {
+      cmn_err (CE_WARN,
+	       "SetCaptureSampleRate(): Requested output rate is below 1/9th of the input rate.\n");
+      return (-1);
+    }
+
+  /*
+   * We can not capture at at rate greater than the Input Rate (48000).
+   * Return an error if an attempt is made to stray outside that limit.
+   */
+  if (ulOutRate > ulInRate)
+    {
+      cmn_err (CE_WARN,
+	       "SetCaptureSampleRate(): Requested output rate is greater than the input rate.");
+      return (-1);
+    }
+  ulTemp1 = ulOutRate << 16;
+  ulCoeffIncr = ulTemp1 / ulInRate;
+  ulTemp1 -= ulCoeffIncr * ulInRate;
+  ulTemp1 <<= 7;
+  ulCoeffIncr <<= 7;
+  ulCoeffIncr += ulTemp1 / ulInRate;
+  ulCoeffIncr ^= 0xFFFFFFFF;
+  ulCoeffIncr++;
+  ulTemp1 = ulInRate << 16;
+  ulPhiIncr = ulTemp1 / ulOutRate;
+  ulTemp1 -= ulPhiIncr * ulOutRate;
+  ulTemp1 <<= 10;
+  ulPhiIncr <<= 10;
+  ulTemp2 = ulTemp1 / ulOutRate;
+  ulPhiIncr += ulTemp2;
+  ulTemp1 -= ulTemp2 * ulOutRate;
+  ulCorrectionPerGOF = ulTemp1 / 200;
+  ulTemp1 -= ulCorrectionPerGOF * 200;
+  ulCorrectionPerSec = ulTemp1;
+  ulInitialDelay = ((ulInRate * 24) + ulOutRate - 1) / ulOutRate;
+  /* Fill in the VariDecimate control block. */
+  WRITE1L (BA1_CSRC, ((ulCorrectionPerSec << 16) & 0xFFFF0000) |
+	   (ulCorrectionPerGOF & 0xFFFF));
+  WRITE1L (BA1_CCI, ulCoeffIncr);
+  WRITE1L (BA1_CD,
+	   (((BA1_VARIDEC_BUF_1 + (ulInitialDelay << 2)) << 16) & 0xFFFF0000)
+	   | 0x80);
+  WRITE1L (BA1_CPI, ulPhiIncr);
+#if 0
+  {
+    unsigned int frameGroupLength, cnt;
+    int rate = ulOutRate;
+
+    frameGroupLength = 1;
+    for (cnt = 2; cnt <= 64; cnt *= 2)
+      {
+	if (((rate / cnt) * cnt) != rate)
+	  frameGroupLength *= 2;
+      }
+    if (((rate / 3) * 3) != rate)
+      {
+	frameGroupLength *= 3;
+      }
+    for (cnt = 5; cnt <= 125; cnt *= 5)
+      {
+	if (((rate / cnt) * cnt) != rate)
+	  frameGroupLength *= 5;
+      }
+
+    WRITE1L (BA1_CFG1, frameGroupLength);
+    WRITE1L (BA1_CFG2, (0x00800000 | frameGroupLength));
+    WRITE1L (BA1_CCST, 0x0000FFFF);
+    WRITE1L (BA1_CSPB, ((65536 * rate) / 24000));
+    WRITE1L ((BA1_CSPB + 4), 0x0000FFFF);
+  }
+#endif
+  return (0);
+}
+
+struct InitStruct
+{
+  unsigned long off;
+  unsigned long val;
+}
+InitArray[] =
+{
+  {
+  0x00000040, 0x3fc0000f}
+  ,
+  {
+  0x0000004c, 0x04800000}
+  ,
+  {
+  0x000000b3, 0x00000780}
+  ,
+  {
+  0x000000b7, 0x00000000}
+  ,
+  {
+  0x000000bc, 0x07800000}
+  ,
+  {
+  0x000000cd, 0x00800000}
+,};
+
+
+/*
+ * "SetCaptureSPValues()" -- Initialize record task values before each
+ *      capture startup.
+ */
+void
+SetCaptureSPValues (cs461x_devc * devc)
+{
+  unsigned i, offset;
+  for (i = 0; i < sizeof (InitArray) / sizeof (struct InitStruct); i++)
+    {
+      offset = InitArray[i].off * 4;	/* 8bit to 32bit offset value */
+      WRITE1L (offset, InitArray[i].val);
+    }
+}
+
+/*ARGSUSED*/
+static int
+cs461x_audio_prepare_for_input (int dev, int bsize, int bcount)
+{
+  cs461x_devc *devc = audio_engines[dev]->devc;
+  cs461x_portc *portc = audio_engines[dev]->portc;
+  dmap_t *dmap = audio_engines[dev]->dmap_in;
+  oss_native_word flags;
+
+  MUTEX_ENTER_IRQDISABLE (devc->mutex, flags);
+
+  /* Start the processor */
+  if (!devc->processor_started)
+    cs461x_start_processor (devc);
+
+  /* Set Capture S/P values */
+  SetCaptureSPValues (devc);
+  /* set the record rate */
+  cs461x_record_rate (devc, portc->speed);
+
+  /* write the buffer address */
+  WRITE1L (BA1_CBA, dmap->dmabuf_phys);
+
+  portc->audio_enabled &= ~PCM_ENABLE_INPUT;
+  portc->trigger_bits &= ~PCM_ENABLE_INPUT;
+  MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+  return 0;
+}
+
+/*ARGSUSED*/
+static int
+cs461x_audio_prepare_for_output (int dev, int bsize, int bcount)
+{
+  cs461x_devc *devc = audio_engines[dev]->devc;
+  cs461x_portc *portc = audio_engines[dev]->portc;
+  dmap_t *dmap = audio_engines[dev]->dmap_out;
+  oss_native_word flags;
+
+  MUTEX_ENTER_IRQDISABLE (devc->mutex, flags);
+  /* Start the processor */
+  if (!devc->processor_started)
+    cs461x_start_processor (devc);
+
+#ifdef USE_SG
+  {
+    unsigned int sg_temp[9], sg_npages = 0;
+    int i;
+    oss_native_word Count, playFormat, tmp, tmp2;
+
+    sg_npages = (dmap->bytes_in_use) / 4096;
+
+    devc->play_sgbuf[0] = dmap->dmabuf_phys;
+    devc->play_sgbuf[1] = 0x00000008;
+
+    for (i = 0; i < sg_npages; i++)
+      {
+	devc->play_sgbuf[2 * i] = dmap->dmabuf_phys + 4096 * i;
+	if (i == sg_npages - 1)
+	  tmp2 = 0xbfff0000;
+	else
+	  tmp2 = 0x80000000 + 8 * (i + 1);
+
+	devc->play_sgbuf[2 * i + 1] = tmp2;
+      }
+    sg_temp[0] = 0x82c0200d;
+    sg_temp[1] = 0xffff0000;
+    sg_temp[2] = devc->play_sgbuf[0];
+    sg_temp[3] = 0x00010600;
+    sg_temp[4] = devc->play_sgbuf[2];
+    sg_temp[5] = 0x80000010;
+    sg_temp[6] = devc->play_sgbuf[0];
+    sg_temp[7] = devc->play_sgbuf[2];
+    sg_temp[8] = (devc->play_sgbuf_phys & 0xffff000) | 0x10;
+
+    for (i = 0; i < sizeof (sg_temp) / 4; i++)
+      WRITE1L ((BA1_PDTC + i * 4), sg_temp[i]);
+
+    WRITE1L (BA1_PBA, dmap->dmabuf_phys);
+
+    cs461x_play_rate (devc, (unsigned int) portc->speed);
+
+    Count = 4;
+    playFormat = READ1L (BA1_PFIE);
+    playFormat &= ~0x0000f03f;
+
+    if ((portc->channels == 2))
+      {
+	playFormat &= ~DMA_RQ_C2_AC_MONO_TO_STEREO;
+	Count *= 2;
+      }
+    else
+      playFormat |= DMA_RQ_C2_AC_MONO_TO_STEREO;
+
+    if ((portc->bits == 16))
+      {
+	playFormat &=
+	  ~(DMA_RQ_C2_AC_8_TO_16_BIT | DMA_RQ_C2_AC_SIGNED_CONVERT);
+	Count *= 2;
+      }
+    else
+      playFormat |= (DMA_RQ_C2_AC_8_TO_16_BIT | DMA_RQ_C2_AC_SIGNED_CONVERT);
+
+    WRITE1L (BA1_PFIE, playFormat);
+
+    tmp = READ1L (BA1_PDTC);
+    tmp &= 0xfffffe00;
+    WRITE1L (BA1_PDTC, tmp | --Count);
+  }
+#else
+  {
+    unsigned int pdtc_value, pfie_value;
+    /* Set the sample rate converter */
+    cs461x_play_rate (devc, (unsigned int) portc->speed);
+
+    pfie_value = READ1L (BA1_PFIE);
+    pfie_value &= ~0x0000f03f;
+
+    pdtc_value = READ1L (BA1_PDTC);
+    pdtc_value &= ~0x000003ff;
+
+    /* Now set the sample size/stereo/mono */
+    if ((portc->bits == 8) && (portc->channels == 1))
+      {
+	pdtc_value |= 0x03;
+	pfie_value |= 0xB000;	/*8bit mono */
+      }
+    if ((portc->bits == 8) && (portc->channels == 2))
+      {
+	pdtc_value |= 0x07;
+	pfie_value |= 0xA000;	/*8bit stereo */
+      }
+    if ((portc->bits == 16) && (portc->channels == 1))
+      {
+	pdtc_value |= 0x07;
+	pfie_value |= 0x2000;	/*16bit mono */
+      }
+    if ((portc->bits == 16) && (portc->channels == 2))
+      {
+	pdtc_value |= 0x0F;
+	pfie_value |= 0x0000;	/*16bit stereo */
+      }
+
+    WRITE1L (BA1_PDTC, pdtc_value);
+    WRITE1L (BA1_PFIE, pfie_value);
+    WRITE1L (BA1_PBA, dmap->dmabuf_phys);
+  }
+#endif
+
+  portc->audio_enabled &= ~PCM_ENABLE_OUTPUT;
+  portc->trigger_bits &= ~PCM_ENABLE_OUTPUT;
+  MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+  return 0;
+}
+
+static int
+cs461x_alloc_buffer (int dev, dmap_t * dmap, int direction)
+{
+
+#ifdef USE_SG
+  int err;
+#else
+  oss_native_word phaddr;
+  cs461x_devc *devc = audio_engines[dev]->devc;
+#endif
+
+  if (dmap->dmabuf != NULL)
+    return 0;
+
+#ifdef USE_SG
+  if ((err = oss_alloc_dmabuf (dev, dmap, direction)) < 0)
+    {
+      cmn_err (CE_WARN, "Failed to allocate a DMA buffer\n");
+      return err;
+    }
+#else
+  dmap->dmabuf =
+    (void *) CONTIG_MALLOC (devc->osdev, 4096, MEMLIMIT_32BITS, &phaddr, dmap->dmabuf_dma_handle);
+  dmap->dmabuf_phys = phaddr;
+# ifdef linux
+  oss_reserve_pages (dmap->dmabuf, dmap->dmabuf + 4096 - 1);
+# endif
+  dmap->buffsize = 4096;
+#endif
+  return 0;
+}
+
+/*ARGSUSED*/
+static int
+cs461x_free_buffer (int dev, dmap_t * dmap, int direction)
+{
+#ifndef USE_SG
+  cs461x_devc *devc = audio_engines[dev]->devc;
+#endif
+#ifdef USE_SG
+  oss_free_dmabuf (dev, dmap);
+  dmap->dmabuf = 0;
+#else
+  if (dmap->dmabuf == NULL)
+    return 0;
+  CONTIG_FREE (devc->osdev, dmap->dmabuf, 4096, dmap->dmabuf_dma_handle);
+# ifdef linux
+  oss_unreserve_pages (dmap->dmabuf, dmap->dmabuf + 4096 - 1);
+# endif
+  dmap->dmabuf = 0;
+#endif
+  return 0;
+
+}
+
+static int
+cs461x_get_buffer_pointer (int dev, dmap_t * dmap, int direction)
+{
+  cs461x_devc *devc = audio_engines[dev]->devc;
+  unsigned int ptr = 0;
+  oss_native_word flags;
+
+  MUTEX_ENTER_IRQDISABLE (devc->low_mutex, flags);
+  if (direction == PCM_ENABLE_OUTPUT)
+    {
+      ptr = READ1L (BA1_PBA) - dmap->dmabuf_phys;
+    }
+  if (direction == PCM_ENABLE_INPUT)
+    {
+      ptr = READ1L (BA1_CBA) - dmap->dmabuf_phys;
+    }
+  MUTEX_EXIT_IRQRESTORE (devc->low_mutex, flags);
+  return ptr;
+}
+
+static audiodrv_t cs461x_audio_driver = {
+  cs461x_audio_open,
+  cs461x_audio_close,
+  cs461x_audio_output_block,
+  cs461x_audio_start_input,
+  cs461x_audio_ioctl,
+  cs461x_audio_prepare_for_input,
+  cs461x_audio_prepare_for_output,
+  cs461x_audio_reset,
+  NULL,
+  NULL,
+  cs461x_audio_reset_input,
+  cs461x_audio_reset_output,
+  cs461x_audio_trigger,
+  cs461x_audio_set_rate,
+  cs461x_audio_set_format,
+  cs461x_audio_set_channels,
+  NULL,
+  NULL,
+  NULL,
+  NULL,
+  cs461x_alloc_buffer,
+  cs461x_free_buffer,
+  NULL,
+  NULL,
+  cs461x_get_buffer_pointer
+};
+
+/***********************MIDI PORT ROUTINES ****************/
+
+/*ARGSUSED*/
+static int
+cs461x_midi_open (int dev, int mode, oss_midi_inputbyte_t inputbyte,
+		  oss_midi_inputbuf_t inputbuf,
+		  oss_midi_outputintr_t outputintr)
+{
+  cs461x_devc *devc = (cs461x_devc *) midi_devs[dev]->devc;
+  oss_native_word flags;
+
+  if (devc->midi_opened)
+    {
+      return OSS_EBUSY;
+    }
+  MUTEX_ENTER_IRQDISABLE (devc->mutex, flags);
+  devc->midi_input_intr = inputbyte;
+  devc->midi_opened = mode;
+
+  /* first reset the MIDI port */
+  PokeBA0 (devc, BA0_MIDCR, 0x10);
+  PokeBA0 (devc, BA0_MIDCR, 0x00);
+
+  /* Now check if we're in Read or Write mode */
+  if (mode & OPEN_READ)
+    {
+      /* enable MIDI Input intr and receive enable */
+      PokeBA0 (devc, BA0_MIDCR, MIDCR_RXE | MIDCR_RIE);
+    }
+
+  if (mode & OPEN_WRITE)
+    {
+      /* enable MIDI transmit enable without interrupt mode */
+      PokeBA0 (devc, BA0_MIDCR, MIDCR_TXE);
+    }
+  PokeBA0 (devc, BA0_HICR, HICR_IEV | HICR_CHGM);
+  MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+  return 0;
+}
+
+/*ARGSUSED*/
+static void
+cs461x_midi_close (int dev, int mode)
+{
+  cs461x_devc *devc = (cs461x_devc *) midi_devs[dev]->devc;
+  oss_native_word flags;
+
+  MUTEX_ENTER_IRQDISABLE (devc->mutex, flags);
+/* Reset the device*/
+  PokeBA0 (devc, BA0_MIDCR, 0x10);
+  PokeBA0 (devc, BA0_MIDCR, 0x00);
+  devc->midi_opened = 0;
+  MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+}
+
+static int
+cs461x_midi_out (int dev, unsigned char midi_byte)
+{
+  cs461x_devc *devc = (cs461x_devc *) midi_devs[dev]->devc;
+  unsigned char uart_stat;
+  oss_native_word flags;
+
+  MUTEX_ENTER_IRQDISABLE (devc->mutex, flags);
+  uart_stat = PeekBA0 (devc, BA0_MIDSR);
+
+/* Check if Transmit buffer full flag is set - if so return */
+  if ((uart_stat & MIDSR_TBF))
+    {
+      MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+      return 0;
+    }
+/* Now put the MIDI databyte in the write port */
+  PokeBA0 (devc, BA0_MIDWP, midi_byte);
+  MUTEX_EXIT_IRQRESTORE (devc->mutex, flags);
+  return 1;
+}
+
+/*ARGSUSED*/
+static int
+cs461x_midi_ioctl (int dev, unsigned cmd, ioctl_arg arg)
+{
+  return OSS_EINVAL;
+}
+
+static midi_driver_t cs461x_midi_driver = {
+  cs461x_midi_open,
+  cs461x_midi_close,
+  cs461x_midi_ioctl,
+  cs461x_midi_out
+};
+
+static int
+init_cs461x (cs461x_devc * devc)
+{
+
+  int my_mixer, my_mixer2, i;
+  unsigned int ulCount = 0;
+  unsigned int ulStatus = 0;
+  unsigned int tmp;
+  int first_dev = 0;
+  int adev;
+  oss_native_word phaddr;
+
+/****************BEGIN HARDWARE INIT*****************/
+  /*
+   * First, blast the clock control register to zero so that the PLL starts
+   * out in a known state, and blast the master serial port control register
+   * to zero so that the serial ports also start out in a known state.
+   */
+  PokeBA0 (devc, BA0_CLKCR1, 0x0);
+  PokeBA0 (devc, BA0_SERMC1, 0x0);
+  oss_udelay (1000);
+  /*
+   * If we are in AC97 mode, then we must set the part to a host controlled
+   * AC-link.  Otherwise, we won't be able to bring up the link.
+   */
+  if (devc->dual_codec)
+    PokeBA0 (devc, BA0_SERACC,
+	     SERACC_HSP | SERACC_TWO_CODECS | SERACC_CODEC_TYPE_2_0);
+  else
+    PokeBA0 (devc, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03);	/* AC97 1.03 */
+
+  /*
+   * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
+   * spec) and then drive it high.  This is done for non AC97 modes since
+   * there might be logic external to the CS461x that uses the ARST# line
+   * for a reset.
+   */
+  PokeBA0 (devc, BA0_ACCTL, 1);
+  oss_udelay (10000);
+  PokeBA0 (devc, BA0_ACCTL, 0);
+  oss_udelay (10000);
+  PokeBA0 (devc, BA0_ACCTL, ACCTL_RSTN);
+  /*
+   * The first thing we do here is to enable sync generation.  As soon
+   * as we start receiving bit clock, we'll start producing the SYNC
+   * signal.
+   */
+  PokeBA0 (devc, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
+
+  /*
+   * Now wait for a short while to allow the AC97 part to start
+   * generating bit clock (so we don't try to start the PLL without an
+   * input clock).
+   */
+  oss_udelay (500000);
+  /*
+   * Set the serial port timing configuration, so that
+   * the clock control circuit gets its clock from the correct place.
+   */
+  PokeBA0 (devc, BA0_SERMC1, SERMC1_PTC_AC97);
+  oss_udelay (500000);
+  /*
+   * Write the selected clock control setup to the hardware.  Do not turn on
+   * SWCE yet (if requested), so that the devices clocked by the output of
+   * PLL are not clocked until the PLL is stable.
+   */
+  PokeBA0 (devc, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
+  PokeBA0 (devc, BA0_PLLM, 0x3a);
+  PokeBA0 (devc, BA0_CLKCR2, CLKCR2_PDIVS_8);
+
+  /*
+   * Power up the PLL.
+   */
+  PokeBA0 (devc, BA0_CLKCR1, CLKCR1_PLLP);
+
+  /*
+   * Wait until the PLL has stabilized.
+   */
+  oss_udelay (100000);
+  /*
+   * Turn on clocking of the core so that we can setup the serial ports.
+   */
+  tmp = PeekBA0 (devc, BA0_CLKCR1) | CLKCR1_SWCE;
+  PokeBA0 (devc, BA0_CLKCR1, tmp);
+
+  /* Clear the FIFOs */
+  clear_serial_fifo (devc);
+  /* PokeBA0 (devc, BA0_SERBSP, 0); */
+
+  /*
+   * Write the serial port configuration to the part.  The master
+   * enable bit is not set until all other values have been written.
+   */
+  PokeBA0 (devc, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
+  PokeBA0 (devc, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
+  PokeBA0 (devc, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
+
+  PokeBA0 (devc, BA0_SERC7, SERC7_ASDI2EN);
+  PokeBA0 (devc, BA0_SERC3, 0);
+  PokeBA0 (devc, BA0_SERC4, 0);
+  PokeBA0 (devc, BA0_SERC5, 0);
+  PokeBA0 (devc, BA0_SERC6, 0);
+
+  oss_udelay (100000);
+
+
+  /* Wait for the codec ready signal from the AC97 codec. */
+  for (ulCount = 0; ulCount < 1000; ulCount++)
+    {
+      /*
+       * First, lets wait a short while to let things settle out a bit,
+       * and to prevent retrying the read too quickly.
+       */
+      oss_udelay (10000);
+      /*
+       * Read the AC97 status register to see if we've seen a CODEC READY
+       * signal from the AC97 codec.
+       */
+      ulStatus = PeekBA0 (devc, BA0_ACSTS);
+      if (ulStatus & ACSTS_CRDY)
+	break;
+    }
+
+  if (!(ulStatus & ACSTS_CRDY))
+    {
+      cmn_err (CE_WARN, "Initialize() Never read Codec Ready from AC97.\n");
+      return 0;
+    }
+
+  if (devc->dual_codec)
+    {
+      for (ulCount = 0; ulCount < 1000; ulCount++)
+	{
+	  /*
+	   *            
+	   * First, lets wait a short while to let things settle out a bit,
+	   * and to prevent retrying the read too quickly.
+	   *
+	   */
+	  oss_udelay (10000);
+	  /*
+	   * Read the AC97 status register to see if we've seen a CODEC READY
+	   * signal from the AC97 codec.
+	   */
+	  ulStatus = PeekBA0 (devc, BA0_ACSTS2);
+	  if (ulStatus & ACSTS_CRDY)
+	    break;
+	}
+
+      if (!(ulStatus & ACSTS_CRDY))
+	{
+	  cmn_err (CE_WARN,
+		   "Initialize() Never read Codec Ready from second AC97.\n");
+	}
+    }
+  /*
+   * Assert the vaid frame signal so that we can start sending commands
+   * to the AC97 codec.
+   */
+  PokeBA0 (devc, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
+  /*
+   * Wait until we've sampled input slots 3 and 4 as valid, meaning that
+   * the codec is pumping ADC data across the AC-link.
+   */
+  for (ulCount = 0; ulCount < 1000; ulCount++)
+    {
+      /*
+       * First, lets wait a short while to let things settle out a bit,
+       * and to prevent retrying the read too quickly.
+       */
+      oss_udelay (10000);
+      /*
+       * Read the input slot valid register and see if input slots 3 and
+       * 4 are valid yet.
+       */
+      ulStatus = PeekBA0 (devc, BA0_ACISV);
+      if ((ulStatus & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
+	break;
+    }
+  /*
+   * Make sure we sampled valid input slots 3 and 4.  If not, then return
+   * an error.
+   */
+  if ((ulStatus & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4))
+    cmn_err (CE_WARN, "Initialize(%x) Never sampled ISV3 & ISV4 from AC97.\n",
+	     (int) ulStatus);
+  /*
+   * Now, assert valid frame and the slot 3 and 4 valid bits.  This will
+   * commense the transfer of digital audio data to the AC97 codec.
+   */
+  PokeBA0 (devc, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
+
+  /* Reset the Processor */
+  cs461x_reset_processor (devc);
+  /* Now download the image */
+  install_ucode (devc);
+
+  devc->processor_started = 0;
+
+  /* Save the play and capture parameters and write 0 to stop DMA */
+  devc->PCTL = READ1L (BA1_PCTL) & 0xFFFF0000;
+  WRITE1L (BA1_PCTL, devc->PCTL & 0x0000FFFF);
+  devc->CCTL = READ1L (BA1_CCTL) & 0x0000FFFF;
+  WRITE1L (BA1_CCTL, devc->CCTL & 0xFFFF0000);
+
+  /*
+   *  Enable interrupts on the part.
+   */
+  PokeBA0 (devc, BA0_HICR, HICR_IEV | HICR_CHGM);
+
+  ulStatus = READ1L (BA1_PFIE);
+  ulStatus &= ~0x0000f03f;
+  WRITE1L (BA1_PFIE, ulStatus);	/* playback interrupt enable */
+
+  ulStatus = READ1L (BA1_CIE);
+  ulStatus &= ~0x0000003f;
+  ulStatus |= 0x00000001;
+  WRITE1L (BA1_CIE, ulStatus);	/* capture interrupt enable */
+
+/****** END OF HARDWARE INIT *****/
+
+  my_mixer =
+    ac97_install (&devc->ac97devc, "CS461x AC97 Mixer", ac97_read, ac97_write,
+		  devc, devc->osdev);
+
+  if (my_mixer >= 0)
+    {
+      devc->mixer_dev = my_mixer;
+      if (devc->subsysid == 0x5053)	/* SantaCruz has dual codec */
+	{
+	  my_mixer2 =
+	    ac97_install (&devc->ac97devc2, "CS4630 AC97 Secondary",
+			  ac97_read2, ac97_write2, devc, devc->osdev);
+	  if (my_mixer2 >= 0)
+	    {
+	      devc->mixer2_dev = my_mixer2;
+	      ac97_write2 (devc, BA0_AC97_6CH_VOL_C_LFE, 0x7FFF);
+	      ac97_write2 (devc, BA0_AC97_6CH_VOL_SURROUND, 0x7FFF);
+	    }
+	}
+    }
+  else
+    return 0;
+
+  /* Turn on amp on the CS4297 on TB/Videologic */
+  if (devc->subsysid == 0x5053)
+    {
+      unsigned short u16PinConfig, u16LogicType, u16ValidSlots, u16Idx;
+      unsigned short u16Status = 0;
+      int i;
+
+
+      ac97_write (devc, 0x26, ac97_read (devc, 0x26) | 0x8000);
+#if 0
+      /* Set SPDIF */
+      PokeBA0 (devc, BA0_ASER_MASTER, 1);	/*ASER_MASTER_ME */
+      WRITE1L (0x8049, 0x00000001);
+#endif
+      /*
+       *  Set GPIO pin's 7 and 8 so that they are configured for output.
+       */
+      u16PinConfig = ac97_read2 (devc, BA0_AC97_GPIO_PIN_CONFIG);
+      u16PinConfig &= 0x27F;
+      ac97_write2 (devc, BA0_AC97_GPIO_PIN_CONFIG, u16PinConfig);
+
+      /*
+       * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
+       */
+      u16LogicType = ac97_read2 (devc, BA0_AC97_GPIO_PIN_TYPE);
+      u16LogicType &= 0x27F;
+      ac97_write2 (devc, BA0_AC97_GPIO_PIN_TYPE, u16LogicType);
+
+      u16ValidSlots = PeekBA0 (devc, BA0_ACOSV);
+      u16ValidSlots |= 0x200;
+      PokeBA0 (devc, BA0_ACOSV, u16ValidSlots);
+
+      /*
+       * Fill slots 12 with the correct value for the GPIO pins. 
+       */
+      for (u16Idx = 0x90; u16Idx <= 0x9F; u16Idx++)
+	{
+
+	  /*
+	   * Initialize the fifo so that bits 7 and 8 are on.
+	   *
+	   * Remember that the GPIO pins in bonzo are shifted by 4 bits to
+	   * the left.  0x1800 corresponds to bits 7 and 8.
+	   */
+	  PokeBA0 (devc, BA0_SERBWP, 0x1800);
+
+	  /*
+	   * Make sure the previous FIFO write operation has completed.
+	   */
+	  for (i = 0; i < 5; i++)
+	    {
+	      u16Status = PeekBA0 (devc, BA0_SERBST);
+	      if (!(u16Status & SERBST_WBSY))
+		{
+		  break;
+		}
+	      oss_udelay (10000);
+	    }
+
+	  /*
+	   * Write the serial port FIFO index.
+	   */
+	  PokeBA0 (devc, BA0_SERBAD, u16Idx);
+
+	  /*
+	   * Tell the serial port to load the new value into the FIFO location.
+	   */
+	  PokeBA0 (devc, BA0_SERBCM, SERBCM_WRC);
+	}
+    }
+  /* Hercules Game Theater Amp */
+  if (devc->subsysid == 0x1681)
+    {
+      PokeBA0 (devc, BA0_EGPIODR, EGPIODR_GPOE2);	/* enable EGPIO2 output */
+      PokeBA0 (devc, BA0_EGPIOPTR, EGPIOPTR_GPPT2);	/* open-drain on output */
+
+    }
+
+#ifdef USE_SG
+  devc->play_sgbuf =
+    (unsigned int *) CONTIG_MALLOC (devc->osdev, 4096, MEMLIMIT_32BITS,
+				    &phaddr, devc->play_sgbuf_dma_handle);
+  if (devc->play_sgbuf == NULL)
+    {
+      cmn_err (CE_WARN,
+	       "cs461x: Failed to allocate play scatter/gather buffer.\n");
+      return 0;
+    }
+  devc->play_sgbuf_phys = phaddr;
+#endif
+
+  for (i = 0; i < MAX_PORTC; i++)
+    {
+      char tmp_name[100];
+      cs461x_portc *portc = &devc->portc[i];
+      int caps = ADEV_AUTOMODE;
+
+      if (i == 0)
+	{
+	  strcpy (tmp_name, devc->chip_name);
+	  caps |= ADEV_DUPLEX;
+	}
+      else
+	{
+	  strcpy (tmp_name, devc->chip_name);
+	  caps |= ADEV_DUPLEX | ADEV_SHADOW;
+	}
+
+      if ((adev = oss_install_audiodev (OSS_AUDIO_DRIVER_VERSION,
+					devc->osdev,
+					devc->osdev,
+					tmp_name,
+					&cs461x_audio_driver,
+					sizeof (audiodrv_t),
+					caps,
+					AFMT_S16_LE | AFMT_U8, devc, -1)) < 0)
+	{
+	  adev = -1;
+	  return 0;
+	}
+      else
+	{
+	  if (i == 0)
+	    first_dev = adev;
+	  audio_engines[adev]->portc = portc;
+	  audio_engines[adev]->mixer_dev = my_mixer;
+	  audio_engines[adev]->rate_source = first_dev;
+	  audio_engines[adev]->min_rate = 5000;
+	  audio_engines[adev]->max_rate = 48000;
+	  audio_engines[adev]->min_block = 4096;
+	  audio_engines[adev]->max_block = 4096;
+	  audio_engines[adev]->caps |= PCM_CAP_FREERATE;
+	  portc->open_mode = 0;
+	  portc->audiodev = adev;
+	  portc->audio_enabled = 0;
+	  portc->trigger_bits = 0;
+#ifdef CONFIG_OSS_VMIX
+	  if (i == 0)
+	     vmix_attach_audiodev(devc->osdev, adev, -1, 0);
+#endif
+	}
+
+    }
+
+#ifndef sparc
+  devc->midi_dev =
+    oss_install_mididev (OSS_MIDI_DRIVER_VERSION, "CS461x",
+			 "CS461x MIDI Port", &cs461x_midi_driver,
+			 sizeof (midi_driver_t),
+			 0, devc, devc->osdev);
+#endif
+  devc->midi_opened = 0;
+  return 1;
+}
+
+int
+oss_cs461x_attach (oss_device_t * osdev)
+{
+  unsigned char pci_irq_line, pci_revision, pci_irq_inta;
+  unsigned short pci_command, vendor, device;
+  unsigned int ioaddr;
+  int err;
+  cs461x_devc *devc;
+
+  DDB (cmn_err (CE_WARN, "Entered CS461x probe routine\n"));
+#if 0
+  if (cs461x_clkrun_fix)
+    while ((osdev = (pci_find_class (0x680 << 8, osdev))))
+
+      {
+	unsigned char pp;
+	unsigned int port, control;
+	unsigned short vendor, device;
+
+	pci_read_config_word (osdev, PCI_VENDOR_ID, &vendor);
+	pci_read_config_word (osdev, PCI_DEVICE_ID, &device);
+
+	if (vendor != 0x8086 || device != 0x7113)
+	  continue;
+
+	pci_read_config_byte (osdev, 0x41, &pp);
+	port = pp << 8;
+	control = INW (devc->osdev, port + 0x10);
+	OUTW (devc->osdev, control | 0x2000, port + 0x10);
+	oss_udelay (100);
+	OUTW (devc->osdev, control & ~0x2000, port + 0x10);
+      }
+#endif
+
+  pci_read_config_word (osdev, PCI_VENDOR_ID, &vendor);
+  pci_read_config_word (osdev, PCI_DEVICE_ID, &device);
+
+  if (vendor != CRYSTAL_VENDOR_ID || device != CRYSTAL_CS461x_ID)
+    return 0;
+
+  if ((devc = PMALLOC (osdev, sizeof (*devc))) == NULL)
+    {
+      cmn_err (CE_WARN, "Out of memory\n");
+      return 0;
+    }
+
+  devc->osdev = osdev;
+  osdev->devc = devc;
+  devc->open_mode = 0;
+
+  oss_pci_byteswap (osdev, 1);
+
+  pci_read_config_byte (osdev, PCI_REVISION_ID, &pci_revision);
+  pci_read_config_word (osdev, PCI_COMMAND, &pci_command);
+  pci_read_config_irq (osdev, PCI_INTERRUPT_LINE, &pci_irq_line);
+  pci_read_config_byte (osdev, PCI_INTERRUPT_LINE + 1, &pci_irq_inta);
+  pci_read_config_dword (osdev, PCI_MEM_BASE_ADDRESS_0, &ioaddr);
+  devc->bar0addr = ioaddr;
+  pci_read_config_dword (osdev, PCI_MEM_BASE_ADDRESS_1, &ioaddr);
+  devc->bar1addr = ioaddr;
+  pci_read_config_word (osdev, PCI_SUBSYSTEM_VENDOR_ID, &devc->subsysid);
+
+  switch (device)
+    {
+    case CRYSTAL_CS461x_ID:
+      devc->chip_name = "Crystal CS461x";
+      break;
+
+    case CRYSTAL_CS4610_ID:
+      devc->chip_name = "Crystal CS4610";
+      break;
+
+    case CRYSTAL_CS4615_ID:
+      devc->chip_name = "Crystal CS4615";
+      break;
+
+    default:
+      devc->chip_name = "CrystalPCI";
+    }
+
+  if (devc->subsysid == 0x5053)
+    {
+      devc->chip_name = "Crystal CS4630";
+      devc->dual_codec = 1;
+    }
+
+  /* activate the device enable bus master/memory space */
+  pci_command |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+  pci_write_config_word (osdev, PCI_COMMAND, pci_command);
+
+  if ((devc->bar0addr == 0) || (devc->bar1addr == 0))
+    {
+      cmn_err (CE_WARN, "Undefined MEMORY I/O address.\n");
+      return 0;
+    }
+
+  if (pci_irq_line == 0)
+    {
+      cmn_err (CE_WARN, "IRQ not assigned by BIOS.\n");
+      return 0;
+    }
+
+  /* Map the shared memory area */
+  devc->bar0virt =
+    (unsigned int *) MAP_PCI_MEM (devc->osdev, 0, devc->bar0addr, 0x2000);
+  devc->bar1virt =
+    (unsigned int *) MAP_PCI_MEM (devc->osdev, 1, devc->bar1addr, 0x40000);
+  devc->dwRegister0 = (unsigned int *) devc->bar0virt;
+  devc->wRegister0 = (unsigned short *) devc->bar0virt;
+  devc->bRegister0 = (unsigned char *) devc->bar0virt;
+  devc->dwRegister1 = (unsigned int *) devc->bar1virt;
+  devc->wRegister1 = (unsigned short *) devc->bar1virt;
+  devc->bRegister1 = (unsigned char *) devc->bar1virt;
+
+  devc->irq = pci_irq_line;
+
+  MUTEX_INIT (devc->osdev, devc->mutex, MH_DRV);
+  MUTEX_INIT (devc->osdev, devc->low_mutex, MH_DRV + 1);
+
+  oss_register_device (osdev, devc->chip_name);
+
+  if ((err = oss_register_interrupts (devc->osdev, 0, cs461xintr, NULL)) < 0)
+    {
+      cmn_err (CE_WARN, "Can't register interrupt handler, err=%d\n", err);
+      return 0;
+    }
+
+  return init_cs461x (devc);	/*Detected */
+}
+
+
+int
+oss_cs461x_detach (oss_device_t * osdev)
+{
+  cs461x_devc *devc = (cs461x_devc *) osdev->devc;
+
+
+  if (oss_disable_device (osdev) < 0)
+    return 0;
+
+  PokeBA0 (devc, BA0_HICR, 0x02);	/*enable intena */
+  cs461x_reset_processor (devc);
+#ifdef USE_SG
+  CONTIG_FREE (devc->osdev, devc->play_sgbuf, 4096, devc->play_sgbuf_dma_handle);
+#endif
+
+  oss_unregister_interrupts (devc->osdev);
+
+  MUTEX_CLEANUP (devc->mutex);
+  MUTEX_CLEANUP (devc->low_mutex);
+
+  UNMAP_PCI_MEM (devc->osdev, 0, devc->bar0addr, devc->bar0virt, 0x2000);
+  UNMAP_PCI_MEM (devc->osdev, 1, devc->bar1addr, devc->bar1virt, 0x40000);
+
+  devc->bar0addr = 0;
+  devc->bar1addr = 0;
+
+  oss_unregister_device (devc->osdev);
+  return 1;
+}
diff --git a/kernel/drv/oss_cs461x/oss_cs461x.man b/kernel/drv/oss_cs461x/oss_cs461x.man
new file mode 100644
index 0000000..11edced
--- /dev/null
+++ b/kernel/drv/oss_cs461x/oss_cs461x.man
@@ -0,0 +1,24 @@
+NAME
+oss_cs461x - Cirrus Logic CS461x/CS4280 audio driver.
+
+DESCRIPTION
+Open Sound System driver for Crystal Semiconductor (Cirrus Logic) CS4280 and
+461x, audio controllers.
+
+CS4280 device characteristics:
+        o 8/16 bit playback/record
+        o mono/stereo playback/recording
+        o 8KHz to 48Khz sample rate.
+
+OPTIONS
+o cs461x_clk_run_fix=0|1 (feature not used anylonger)
+Certain IBM Thinkpads required the CLK_RUN bit flipped in order to wake up
+the audio device. 
+
+
+FILES
+CONFIGFILEPATH/oss_cs461x.conf Device configuration file
+
+AUTHOR
+4Front Technologies
+