diff options
Diffstat (limited to 'src/cmd/5l')
| -rw-r--r-- | src/cmd/5l/asm.c | 44 | ||||
| -rw-r--r-- | src/cmd/5l/l.h | 1 | ||||
| -rw-r--r-- | src/cmd/5l/optab.c | 2 |
3 files changed, 18 insertions, 29 deletions
diff --git a/src/cmd/5l/asm.c b/src/cmd/5l/asm.c index 34565629f..7163997c0 100644 --- a/src/cmd/5l/asm.c +++ b/src/cmd/5l/asm.c @@ -637,13 +637,6 @@ wput(int32 l) cflush(); } -void -wputl(ushort w) -{ - cput(w); - cput(w>>8); -} - void hput(int32 l) @@ -672,20 +665,6 @@ lput(int32 l) } void -lputl(int32 l) -{ - - cbp[3] = l>>24; - cbp[2] = l>>16; - cbp[1] = l>>8; - cbp[0] = l; - cbp += 4; - cbc -= 4; - if(cbc <= 0) - cflush(); -} - -void cflush(void) { int n; @@ -1491,15 +1470,24 @@ if(debug['G']) print("%ux: %s: arm %d %d %d\n", (uint32)(p->pc), p->from.sym->na o1 |= (p->scond & C_SCOND) << 28; break; case 80: /* fmov zfcon,freg */ - if((p->scond & C_SCOND) != C_SCOND_NONE) - diag("floating point cannot be conditional"); // cant happen - o1 = 0xf3000110; // EOR 64 - - // always clears the double float register + if(p->as == AMOVD) { + o1 = 0xeeb00b00; // VMOV imm 64 + o2 = oprrr(ASUBD, p->scond); + } else { + o1 = 0x0eb00a00; // VMOV imm 32 + o2 = oprrr(ASUBF, p->scond); + } + v = 0x70; // 1.0 r = p->to.reg; - o1 |= r << 0; + + // movf $1.0, r + o1 |= (p->scond & C_SCOND) << 28; o1 |= r << 12; - o1 |= r << 16; + o1 |= (v&0xf) << 0; + o1 |= (v&0xf0) << 12; + + // subf r,r,r + o2 |= r | (r<<16) | (r<<12); break; case 81: /* fmov sfcon,freg */ o1 = 0x0eb00a00; // VMOV imm 32 diff --git a/src/cmd/5l/l.h b/src/cmd/5l/l.h index c31028416..e42be4e98 100644 --- a/src/cmd/5l/l.h +++ b/src/cmd/5l/l.h @@ -410,6 +410,7 @@ Sym* lookup(char*, int); void cput(int); void hput(int32); void lput(int32); +void lputb(int32); void lputl(int32); void* mysbrk(uint32); void names(void); diff --git a/src/cmd/5l/optab.c b/src/cmd/5l/optab.c index 9ad0193ac..8b3135e06 100644 --- a/src/cmd/5l/optab.c +++ b/src/cmd/5l/optab.c @@ -236,7 +236,7 @@ Optab optab[] = { ALDREX, C_SOREG,C_NONE, C_REG, 77, 4, 0 }, { ASTREX, C_SOREG,C_REG, C_REG, 78, 4, 0 }, - { AMOVF, C_ZFCON,C_NONE, C_FREG, 80, 4, 0 }, + { AMOVF, C_ZFCON,C_NONE, C_FREG, 80, 8, 0 }, { AMOVF, C_SFCON,C_NONE, C_FREG, 81, 4, 0 }, { ACMPF, C_FREG, C_REG, C_NONE, 82, 8, 0 }, |